Datasheet AD9255 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter |
| Seiten / Seite | 45 / 5 — AD9255. Data Sheet. SPECIFICATIONS ADC DC SPECIFICATIONS. Table 1. … |
| Revision | C |
| Dateiformat / Größe | PDF / 1.8 Mb |
| Dokumentensprache | Englisch |
AD9255. Data Sheet. SPECIFICATIONS ADC DC SPECIFICATIONS. Table 1. AD9255BCPZ-801 AD92. 55BCPZ-1051 AD92. 55BCPZ-1251. Parameter Temp
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AD9255 Data Sheet SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 1. AD9255BCPZ-801 AD92 55BCPZ-1051 AD92 55BCPZ-1251 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.05 ±0.25 ±0.05 ±0.25 ±0.05 ±0.25 % FSR Gain Error Full ±0.2 ±2.5 ±0.2 ±2.5 ±0.4 ±2.5 % FSR Differential Nonlinearity (DNL)2 Full ±0.4 ±0.4 ±0.45 LSB 25°C ±0.2 ±0.2 ±0.25 LSB Integral Nonlinearity (INL)2 Full ±0.9 ±0.9 ±1.2 LSB 25°C ±0.35 ±0.45 ±0.7 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C Gain Error Full ±15 ±15 ±15 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full +8 ±12 +8 ±12 +8 ±12 mV Load Regulation at 1.0 mA Full 3 3 3 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.62 0.63 0.61 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance3 F ull 8 8 8 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V REFERENCE INPUT RESISTANCE Full 6 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V SVDD Full 1.7 3.5 1.7 3.5 1.7 3.5 V Supply Current IAVDD2 Full 126 131 169 176 194 202 mA IDRVDD2 (1.8 V CMOS) Full 13 19 23 mA IDRVDD2 (1.8 V LVDS) Full 39 42 44 mA POWER CONSUMPTION DC Input Full 239 248 321 332 371 382 mW Sine Wave Input2 CMOS Output Mode Full 252 338 391 mW LVDS Output Mode Full 306 384 437 mW Standby Power4 Full 54 54 54 mW Power-Down Power Full 0.05 0.15 0.05 0.15 0.05 0.15 mW 1 The suffix following the part number refers to the model found in the Ordering Guide section. 2 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input, the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND). Rev. C | Page 4 of 44 Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide
AD9255 Data Sheet SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 1. AD9255BCPZ-801 AD92 55BCPZ-1051 AD92 55BCPZ-1251 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.05 ±0.25 ±0.05 ±0.25 ±0.05 ±0.25 % FSR Gain Error Full ±0.2 ±2.5 ±0.2 ±2.5 ±0.4 ±2.5 % FSR Differential Nonlinearity (DNL)2 Full ±0.4 ±0.4 ±0.45 LSB 25°C ±0.2 ±0.2 ±0.25 LSB Integral Nonlinearity (INL)2 Full ±0.9 ±0.9 ±1.2 LSB 25°C ±0.35 ±0.45 ±0.7 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C Gain Error Full ±15 ±15 ±15 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full +8 ±12 +8 ±12 +8 ±12 mV Load Regulation at 1.0 mA Full 3 3 3 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.62 0.63 0.61 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance3 F ull 8 8 8 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V REFERENCE INPUT RESISTANCE Full 6 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V SVDD Full 1.7 3.5 1.7 3.5 1.7 3.5 V Supply Current IAVDD2 Full 126 131 169 176 194 202 mA IDRVDD2 (1.8 V CMOS) Full 13 19 23 mA IDRVDD2 (1.8 V LVDS) Full 39 42 44 mA POWER CONSUMPTION DC Input Full 239 248 321 332 371 382 mW Sine Wave Input2 CMOS Output Mode Full 252 338 391 mW LVDS Output Mode Full 306 384 437 mW Standby Power4 Full 54 54 54 mW Power-Down Power Full 0.05 0.15 0.05 0.15 0.05 0.15 mW 1 The suffix following the part number refers to the model found in the Ordering Guide section. 2 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input, the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND). Rev. C | Page 4 of 44 Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide