Datasheet AD7195 (Analog Devices) - 7

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AD7195 Data Sheet TIMING CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2. Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments1, 2
READ AND WRITE OPERATIONS t3 100 ns min SCLK high pulse width t4 100 ns min SCLK low pulse width READ OPERATION t1 0 ns min CS falling edge to DOUT/RDY active time 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t 3 2 0 ns min SCLK active edge to data valid delay4 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t 5, 6 5 10 ns min Bus relinquish time after CS inactive edge 80 ns max t6 0 ns min SCLK inactive edge to CS inactive edge t7 10 ns min SCLK inactive edge to DOUT/RDY high WRITE OPERATION t8 0 ns min CS falling edge to SCLK active edge setup time4 t9 30 ns min Data valid to SCLK edge setup time t10 25 ns min Data valid to SCLK edge hold time t11 0 ns min CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. Rev. A | Page 6 of 44 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter AC Excitation Serial Interface Clock Temperature Sensor Calibration ANALOG INPUT CHANNEL PGA REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS AC EXCITATION CHANNEL SEQUENCER Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION CLOCK ENABLE PARITY TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE