Datasheet AD7195 (Analog Devices)

4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation Data Sheet AD7195 FEATURES Chromatography AC or DC sensor excitation PLC/DCS analog input modules RMS noise: 8.5 nV at 4.7 Hz (gain = 128) Data acquisition 16 noise-free bits at 2.4 kHz (gain = 128) Medical and scientific instrumentation Up to 22.5 noise-free bits (gain = 1) GENERAL DESCRIPTION Offset drift: 5 nV/°C
The AD7195 is a low noise, complete analog front end for high
Gain drift: 1 ppm/°C
precision measurement applications. It contains a low noise,
Specified drift over time
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
2 differential/4 pseudo differential input channels Automatic channel sequencer
The on-chip low noise gain stage means that signals of small
Programmable gain (1 to 128)
amplitude can be interfaced directly to the ADC. The AD7195
Output data rate: 4.7 Hz to 4.8 kHz
contains ac excitation, which is used to remove dc-induced
Internal or external clock
offsets from bridge sensors.
Simultaneous 50 Hz/60 Hz rejection
The device can be configured to have two differential inputs or
Power supply
four pseudo differential inputs. The on-chip channel sequencer
AVDD: 4.75 V to 5.25 V
al ows several channels to be enabled, and the AD7195 sequentially
DVDD: 2.7 V to 5.25 V
converts on each enabled channel. This simplifies communication
Current: 6 mA
with the part. The on-chip 4.92 MHz clock can be used as the
Temperature range: –40°C to +105°C
clock source to the ADC or, alternatively, an external clock or
Package: 32-lead LFCSP
crystal can be used. The output data rate from the part can be
INTERFACE
varied from 4.7 Hz to 4.8 kHz. The device has two digital filter options. The choice of filter
3-wire serial
affects the rms noise/noise-free resolution at the programmed
SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK
output data rate, the settling time, and the 50 Hz/60 Hz rejec- tion. For applications that require al conversions to be settled,
APPLICATIONS
the AD7195 includes a zero latency feature.
Weigh scales
The part operates with a 5 V analog power supply and a digital
Strain gage transducers
power supply from 2.7 V to 5.25 V. It consumes a current of
Pressure measurement
6 mA. It is housed in a 32-lead LFCSP package.
Temperature measurement FUNCTIONAL BLOCK DIAGRAM AV DV DD AGND DD DGND REFIN(+) REFIN(–) REFERENCE DETECT AIN1 AVDD AIN2 AIN3 SERIAL DOUT/RDY AIN4 INTERFACE MUX DIN Σ-Δ PGA AND AINCOM ADC CONTROL SCLK LOGIC CS SYNC BPDSW AGND TEMP SENSOR AC EXCITATION CLOCK CIRCUITRY AD7195 CLOCK
001
ACX1 ACX1 ACX2 ACX2 MCLK1 MCLK2
08771- Figure 1.
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Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter AC Excitation Serial Interface Clock Temperature Sensor Calibration ANALOG INPUT CHANNEL PGA REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS AC EXCITATION CHANNEL SEQUENCER Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION CLOCK ENABLE PARITY TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE