Datasheet AD9262 (Analog Devices) - 5

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AD9262 AC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted.
Table 2. AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 600 kHz2 Full 86 89 dB fIN = 1.2 MHz3 Full 89 83 86 dB fIN = 2.4 MHz4 Full 89 86 81 83 dB fIN = 4.2 MHz 25°C 86 83 dB fIN = 8.4 MHz 25°C 83 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 600 kHz 25°C Bits fIN = 1.2 MHz 25°C 14.5 Bits fIN = 2.4 MHz 25°C 14.5 14 Bits fIN = 4.2 MHz 25°C 14 13.5 Bits fIN = 8.4 MHz 25°C 13.5 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 600 kHz2 Full −87 −80 dBc fIN = 1.2 MHz3 Full −87 −87 −80 dBc fIN = 2.4 MHz4 Full <−120 −87 −87 −80 dBc fIN = 4.2 MHz 25°C <−120 −87 dBc fIN = 8.4 MHz 25°C <−120 dBc NOISE SPECTRAL DENSITY (NSD) AIN = −2 dBFS Full −154.3 −152 −155 −152 −155 −153 dBFS/Hz AIN = −40 dBFS Full −155.4 −154 −156 −154.5 −156 −154.5 dBFS/Hz NOISE FIGURE5 25°C 15.6 15 15 dB TWO-TONE SFDR fIN1 = 1.8 MHz @ −8 dBFS, fIN2 = 2.1 MHz @ −8 dBFS 25°C −92 dBc fIN1 = 2.1 MHz @ −8 dBFS, fIN2 = 2.4 MHz @ −8 dBFS 25°C −93 −93 dBc fIN1 = 3.7 MHz @ −8 dBFS, fIN2 = 4.2 MHz @ −8 dBFS 25°C −92.5 dBc fIN1 = 7.2 MHz @ −8 dBFS, fIN2 = 8.4 MHz @ −8 dBFS 25°C −92.5 dBc CROSSTALK6 25°C −110 −110 −110 dB ANALOG INPUT BANDWIDTH 25°C 2.5 5 10 MHz APERTURE JITTER 25°C 1 1 1 ps rms 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Data guaranteed over the full temperature range for the AD9262BCPZ only. 3 Data guaranteed over the full temperature range for the AD9262BCPZ-5 only. 4 Data guaranteed over the full temperature range for the AD9262BCPZ-10 only. 5 Noise figure with respect to 50 Ω. AD9262 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition. 6 Crosstalk measured with an input signal on both channels at different frequencies and the leakage of one on to the other. Rev. A | Page 4 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Digital Outputs Digital Output Format Interleaved Outputs Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide