AD9262PIN CONFIGURATION AND FUNCTION DESCRIPTIONST+DBDTFDAADEKNDNDD–B+–+NNDILEDNNDNDSBCLCGAGAVVIVIAVCFVRAVVIVIAVAGRECS64636261605958575655545352515049CLK– 1PIN 148 SCLKINDICATORCVDD 247 SDIOD0B 346 ORAD1B 445 D15AD2B 544 D14AAD9262DVDD 643 DVDDDGND 7CMOS OUTPUTS42 DGNDDRVDD 841 DRVDDD3B 9TOP VIEW40 D13AD4B 10(Not to Scale)39 D12AD5B 1138 D11AD6B 1237 D10AD7B 1336 D9AD8B 1435 D8AD9B 1534 D7AD10B 1633 D6A17181920212223242526272829303132BAAAAAA1BDONDDDD1D0D1D2D3D4D5D12BD13BD14BD15BORVDDCDGDVDRNOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THELFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB 3 INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING 00 2- THE THERMAL CAPACITY OF THE PACKAGE. 77 07 Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No.MnemonicDescription 1 CLK− Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3 to 5, 9 to 21 D0B to D15B Channel B Data Output Pins. D0B is the LSB and D15B is the MSB. 6, 25, 43 DVDD Digital Supply (1.8 V). 7, 24, 42 DGND Digital Ground. 8, 23, 41 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Overrange Indicator. 26 DCO Data Clock Output. 27 to 40, 44, 45 D0A to D15A Channel A Data Output Pins. D0A is the LSB and D15A is the MSB. 46 ORA Channel A Overrange Indicator. 47 SDIO Serial Port Interface Data Input/Output. 48 SCLK Serial Port Interface Clock. 49 CSB Serial Port Interface Chip Select Active Low. 50 RESET Chip Reset. 51, 62 AGND Analog Ground. 52, 55, 58, 61 AVDD Analog Supply (1.8 V). 53 VIN+A Channel A Analog Input (+). 54 VIN−A Channel A Analog Input (−). 56 VREF Voltage Reference Input. 57 CFILT Noise Limiting Filter Capacitor. 59 VIN+B Channel B Analog Input (+). 60 VIN−B Channel B Analog Input (−). 63 CGND Clock Ground. 64 CLK+ Clock Input (+). 65 (EPAD) Exposed pad (EPAD) Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The exposed pad must be soldered to ground. Rev. A | Page 9 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Digital Outputs Digital Output Format Interleaved Outputs Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide