Datasheet AD9628 (Analog Devices) - 4

Data Sheet AD9628 GENERAL DESCRIPTION
The AD9628 is a monolithic, dual-channel, 1.8 V supply, 12-bit, A differential clock input controls al internal conversion cycles. 125 MSPS/105 MSPS analog-to-digital converter (ADC). It An optional duty cycle stabilizer (DCS) compensates for wide features a high performance sample-and-hold circuit and on- variations in the clock duty cycle while maintaining excel ent chip voltage reference. overal ADC performance. The product uses multistage differential pipeline architecture The digital output data is presented in offset binary, Gray code, or with output error correction logic to provide 12-bit accuracy at twos complement format. A data output clock (DCO) is provided 125 MSPS data rates and to guarantee no missing codes over the for each ADC channel to ensure proper latch timing with receiving ful operating temperature range. logic. 1.8 V CMOS or LVDS output logic levels are supported. The ADC contains several features designed to maximize Output data can also be multiplexed onto a single output bus. flexibility and minimize system cost, such as programmable The AD9628 is available in a 64-lead RoHS-compliant LFCSP clock and data alignment and programmable digital test pattern and is specified over the industrial temperature range (−40°C to generation. The available digital test patterns include built-in +85°C). deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. C | Page 3 of 42 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9628-125 AD9628-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE