Datasheet AD9628 (Analog Devices)

12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9628 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD AGND SDIO SCLK CSB 1.8 V CMOS or LVDS outputs SNR = 71.2 dBFS @ 70 MHz SPI ORA SFDR = 93 dBc @ 70 MHz R Low power: 101 mW/channel @ 125 MSPS FFE VIN+A PROGRAMMING DATA U D11A LVDS Differential analog input with 650 MHz bandwidth ADC S/ VIN–A T B U D0A MO IF sampling frequencies to 200 MHz C TPOU On-chip voltage reference and sample-and-hold circuit DCOA VREF 2 V p-p differential analog input TION SENSE DRVDD DNL = ±0.25 LSB AD9628 X OP VCM REF U Serial port control options SELECT M RBIAS ORB R Offset binary, Gray code, or twos complement data format FFE U D11B Optional clock duty cycle stabilizer VIN–B ADC LVDS S/ T B Integer 1-to-8 input clock divider VIN+B U D0B MO C TP Data output multiplex option OU DCOB Built-in selectable digital test pattern generation Energy-saving power-down modes DIVIDE DUTY CYCLE MODE 1 TO 8 STABILIZER CONTROLS Data clock out with programmable clock and data alignment CLK+ CLK– SYNC DCS PDWN DFS OEB NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
001
APPLICATIONS SEE FIGURE 7 FOR LVDS PIN NAMES.
09976-
Communications
Figure 1.
Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, PRODUCT HIGHLIGHTS CDMA2000, WiMAX, TD-SCDMA
1. The AD9628 operates from a single 1.8 V analog power
I/Q demodulation systems
supply and features a separate digital output driver supply
Smart antenna systems
to accommodate 1.8 V CMOS or LVDS logic families.
Broadband data applications
2. The patented sample-and-hold circuit maintains excel ent
Battery-powered instruments
performance for input frequencies up to 200 MHz and is
Hand-held scope meters
designed for low cost, low power, and ease of use.
Portable medical imaging
3. A standard serial port interface supports various product
Ultrasound
features and functions, such as data output formatting,
Radar/LIDAR
internal clock divider, power-down, DCO/data timing and offset adjustments. 4. The AD9628 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9650/AD9269/ AD9268 16-bit ADC, the AD9258/AD9251/AD9648 14-bit ADCs, the AD9231 12-bit ADC, and the AD9608/AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9628-125 AD9628-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE