Datasheet AD9628 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter |
| Seiten / Seite | 43 / 3 — AD9628. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 11/15—Rev. B to … |
| Revision | C |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
AD9628. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 11/15—Rev. B to Rev. C. 8/15—Rev. A to Rev. B. 11/14—Rev. 0 to Rev. A
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AD9628 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 27 Applications ... 1 Clock Input Considerations .. 28 Functional Block Diagram .. 1 Channel/Chip Synchronization .. 30 Product Highlights ... 1 Power Dissipation and Standby Mode .. 30 Revision History ... 2 Digital Outputs ... 31 General Description ... 3 Timing.. 31 Specifications ... 4 Output Test .. 32 DC Specifications ... 4 Output Test Modes ... 32 AC Specifications ... 5 Serial Port Interface (SPI) .. 33 Digital Specifications ... 6 Configuration Using the SPI ... 33 Switching Specifications .. 8 Hardware Interface ... 34 Timing Specifications .. 9 Configuration Without the SPI .. 34 Absolute Maximum Ratings .. 12 SPI Accessible Features .. 34 Thermal Characteristics .. 12 Memory Map .. 35 ESD Caution .. 12 Reading the Memory Map Register Table ... 35 Pin Configurations and Function Descriptions ... 13 Memory Map Register Table ... 36 Typical Performance Characteristics ... 19 Memory Map Register Descriptions .. 39 AD9628-125 .. 19 Applications Information .. 41 AD9628-105 .. 22 Design Guidelines .. 41 Equivalent Circuits ... 24 Outline Dimensions ... 42 Theory of Operation .. 25 Ordering Guide .. 42 ADC Architecture .. 25 Analog Input Considerations .. 25
REVISION HISTORY 11/15—Rev. B to Rev. C
Changes to Differential Input Configurations Section ... 26 Changed AD9516 to AD9516-0/AD9516-1/AD9516-2/ Deleted Figure 48; Renumbered Sequentially .. 27 AD9516-3/AD9516-4/AD9516-5, and AD9517 to AD9517-0/ Change to Clock Input Options Section ... 28 AD9517-1/AD9517-2/AD9517-3/AD9517-4 .. Throughout Changed Built-In Self-Test (BIST) and Output Test Mode Change to Figure 3 ... 10 Section to Output Test Section ... 32 Deleted Built-In Self-Test (BIST) Section ... 32
8/15—Rev. A to Rev. B
Change to Configuration Without the SPI Section ... 34 Changes to Features Section and Product Highlights Section ... 1 Changes to Channel-Specific Registers Section ... 35 Changes to General Description Section .. 3 Changes to Table 18 ... 37 Changes to Aperture Uncertainty (Jitter, tJ) Parameter, Changes to Bit 7—OEB Pin Enable Section.. 40 Table 4 .. 8 Added Clock Stability Considerations Section... 41 Changes to Table 6 .. 12 Updated Outline Dimensions ... 42 Changes to Table 7 .. 12 Changes to RBIAS Pin Description and OEB Pin Description,
11/14—Rev. 0 to Rev. A
Table 8 .. 13 Changes to Table 10 ... 18 Changes to RBIAS Pin Description and OEB Pin Description, Change to Figure 61 Caption .. 30 Table 9 .. 15 Updated Outline Dimensions ... 42 Changes to RBIAS Pin Description and OEB Pin Description, Table 10 .. 17
7/11—Revision 0: Initial Version
Changes to Figure 35 .. 24 Rev. C | Page 2 of 42 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9628-125 AD9628-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE
AD9628 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 27 Applications ... 1 Clock Input Considerations .. 28 Functional Block Diagram .. 1 Channel/Chip Synchronization .. 30 Product Highlights ... 1 Power Dissipation and Standby Mode .. 30 Revision History ... 2 Digital Outputs ... 31 General Description ... 3 Timing.. 31 Specifications ... 4 Output Test .. 32 DC Specifications ... 4 Output Test Modes ... 32 AC Specifications ... 5 Serial Port Interface (SPI) .. 33 Digital Specifications ... 6 Configuration Using the SPI ... 33 Switching Specifications .. 8 Hardware Interface ... 34 Timing Specifications .. 9 Configuration Without the SPI .. 34 Absolute Maximum Ratings .. 12 SPI Accessible Features .. 34 Thermal Characteristics .. 12 Memory Map .. 35 ESD Caution .. 12 Reading the Memory Map Register Table ... 35 Pin Configurations and Function Descriptions ... 13 Memory Map Register Table ... 36 Typical Performance Characteristics ... 19 Memory Map Register Descriptions .. 39 AD9628-125 .. 19 Applications Information .. 41 AD9628-105 .. 22 Design Guidelines .. 41 Equivalent Circuits ... 24 Outline Dimensions ... 42 Theory of Operation .. 25 Ordering Guide .. 42 ADC Architecture .. 25 Analog Input Considerations .. 25
REVISION HISTORY 11/15—Rev. B to Rev. C
Changes to Differential Input Configurations Section ... 26 Changed AD9516 to AD9516-0/AD9516-1/AD9516-2/ Deleted Figure 48; Renumbered Sequentially .. 27 AD9516-3/AD9516-4/AD9516-5, and AD9517 to AD9517-0/ Change to Clock Input Options Section ... 28 AD9517-1/AD9517-2/AD9517-3/AD9517-4 .. Throughout Changed Built-In Self-Test (BIST) and Output Test Mode Change to Figure 3 ... 10 Section to Output Test Section ... 32 Deleted Built-In Self-Test (BIST) Section ... 32
8/15—Rev. A to Rev. B
Change to Configuration Without the SPI Section ... 34 Changes to Features Section and Product Highlights Section ... 1 Changes to Channel-Specific Registers Section ... 35 Changes to General Description Section .. 3 Changes to Table 18 ... 37 Changes to Aperture Uncertainty (Jitter, tJ) Parameter, Changes to Bit 7—OEB Pin Enable Section.. 40 Table 4 .. 8 Added Clock Stability Considerations Section... 41 Changes to Table 6 .. 12 Updated Outline Dimensions ... 42 Changes to Table 7 .. 12 Changes to RBIAS Pin Description and OEB Pin Description,
11/14—Rev. 0 to Rev. A
Table 8 .. 13 Changes to Table 10 ... 18 Changes to RBIAS Pin Description and OEB Pin Description, Change to Figure 61 Caption .. 30 Table 9 .. 15 Updated Outline Dimensions ... 42 Changes to RBIAS Pin Description and OEB Pin Description, Table 10 .. 17
7/11—Revision 0: Initial Version
Changes to Figure 35 .. 24 Rev. C | Page 2 of 42 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9628-125 AD9628-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE