Datasheet LTC2265-14, LTC2264-14, LTC2263-14 (Analog Devices) - 5

LTC2265-14/ LTC2264-14/LTC2263-14
DIGITAL INPUTS AND OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Single-Ended Encode Mode (ENC– Tied to GND)
VIH High Level Input Voltage VDD = 1.8V l 1.2 V VIL Low Level Input Voltage VDD = 1.8V l 0.6 V VIN Input Voltage Range ENC+ to GND l 0 3.6 V RIN Input Resistance (See Figure 11) 30 kΩ CIN Input Capacitance 3.5 pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage VDD = 1.8V l 1.3 V VIL Low Level Input Voltage VDD = 1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 µA CIN Input Capacitance 3 pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA COUT Output Capacitance 3 pF
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode l 247 350 454 mV 100Ω Differential Load, 1.75mA Mode l 125 175 250 mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.250 1.375 V 100Ω Differential Load, 1.75mA Mode l 1.125 1.250 1.375 V RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2265-14 LTC2264-14 LTC2263-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 84 98 53 63 42 50 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode 11 10 10 mA 1-Lane Mode, 3.5mA Mode 20 19 18 mA 2-Lane Mode, 1.75mA Mode l 15 18 15 17 14 17 mA 2-Lane Mode, 3.5mA Mode l 28 32 28 31 27 31 mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode 171 113 94 mW 1-Lane Mode, 3.5mA Mode 187 130 108 mW 2-Lane Mode, 1.75mA Mode l 178 209 122 144 101 121 mW 2-Lane Mode, 3.5mA Mode l 202 234 146 169 124 146 mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 60 60 60 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No Increase for Sleep Mode) 22654314fb 5 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts