Datasheet LTC2265-14, LTC2264-14, LTC2263-14 (Analog Devices)

LTC2265-14/ LTC2264-14/LTC2263-14 14-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs
FEATURES DESCRIPTION
n
2-Channel Simultaneous Sampling ADC
The LTC®2265-14/LTC2264-14/LTC2263-14 are 2-channel, n
73.7dB SNR
simultaneous sampling 14-bit A/D converters designed n
90dB SFDR
for digitizing high frequency, wide dynamic range signals. n Low Power: 171mW/113mW/94mW Total They are perfect for demanding communications applica- n 85mW/56mW/47mW per Channel tions with AC performance that includes 73.7dB SNR and n Single 1.8V Supply 90dB spurious free dynamic range (SFDR). Ultralow jitter n Serial LVDS Outputs: 1 or 2 Bits per Channel of 0.15psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 800MHz Full Power Bandwidth S/H DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is a low 1.2LSBRMS. n Pin Compatible 14-Bit and 12-Bit Versions n 40-Pin (6mm × 6mm) QFN Package The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS
APPLICATIONS
drivers have optional internal termination and adjustable n Communications output levels to ensure clean signal integrity. n Cellular Base Stations The ENC+ and ENC– inputs may be driven differentially n Software Defined Radios or single-ended with a sine wave, PECL, LVDS, TTL, or n Portable Medical Imaging CMOS inputs. An internal clock duty cycle stabilizer n Multichannel Data Acquisition allows high performance at full speed for a wide range of n Nondestructive Testing clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION LTC2265-14, 65Msps,
1.8V 1.8V
2-Tone FFT, fIN = 70MHz and 75MHz
VDD OVDD 0 CH.1 + –10 OUT1A ANALOG S/H 14-BIT –20 INPUT – ADC CORE OUT1B –30 –40 CH.2 + DATA SERIALIZED 14-BIT OUT2A ANALOG S/H SERIALIZER LVDS –50 ADC CORE INPUT – OUT2B OUTPUTS –60 DATA –70 CLOCK ENCODE AMPLITUDE (dBFS) –80 OUT INPUT PLL FRAME –90 –100 –110 GND OGND –120 0 10 20 30 226514 TA01 FREQUENCY (MHz) 226514 TA02 22654314fb 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts