Datasheet LTC2265-14, LTC2264-14, LTC2263-14 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 65Msps Low Power Dual ADCs |
| Seiten / Seite | 32 / 6 — TIMING CHARACTERISTICS. The. denotes the specifications which apply over … |
| Dateiformat / Größe | PDF / 1.5 Mb |
| Dokumentensprache | Englisch |
TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating temperature
Modelllinie für dieses Datenblatt
- LTC2263CUJ-14#PBF LTC2263CUJ-14#PBF LTC2263CUJ-14#TRPBF LTC2263CUJ-14#TRPBF LTC2263IUJ-14#PBF LTC2263IUJ-14#PBF LTC2263IUJ-14#TRPBF LTC2263IUJ-14#TRPBF
Textversion des Dokuments
LTC2265-14/ LTC2264-14/LTC2263-14
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2265-14 LTC2264-14 LTC2263-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10, 11) l 5 65 5 40 5 25 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER Serial Data Bit Period Two Lanes, 16-Bit Serialization 1 / (8 • fS) s Two Lanes, 14-Bit Serialization 1 / (7 • fS) Two Lanes, 12-Bit Serialization 1 / (6 • fS) One Lane, 16-Bit Serialization 1 / (16 • fS) One Lane, 14-Bit Serialization 1 / (14 • fS) One Lane, 12-Bit Serialization 1 / (12 • fS) tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-to-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Set-Up Time l 5 ns tH SCK to CS Set-Up Time l 5 ns tDS SDI Set-Up Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when
Note 2:
All voltage values are with respect to GND with GND and OGND the output code flickers between 00 0000 0000 0000 and 11 1111 1111 shorted (unless otherwise noted). 1111 in 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2265), 40MHz of greater than 100mA below GND or above VDD without latchup. (LTC2264), or 25MHz (LTC2263), 2-lane output mode, ENC+ = single-
Note 4:
When these pin voltages are taken below GND they will be ended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential clamped by internal diodes. When these pin voltages are taken above VDD drive, unless otherwise noted. The supply current and power dissipation they will not be clamped by internal diodes. This product can handle input specifications are totals for the entire chip, not per channel. currents of greater than 100mA below GND without latchup.
Note 10:
Recommended operating conditions.
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2265), 40MHz
Note 11:
The maximum sampling frequency depends on the speed grade (LTC2264), or 25MHz (LTC2263), 2-lane output mode, differential ENC+/ of the part and also which serialization mode is used. The maximum serial ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless data rate is 1000Mbps, so tSER must be greater than or equal to 1ns. otherwise noted. 22654314fb 6 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2265-14 LTC2264-14 LTC2263-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10, 11) l 5 65 5 40 5 25 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100 ns Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER Serial Data Bit Period Two Lanes, 16-Bit Serialization 1 / (8 • fS) s Two Lanes, 14-Bit Serialization 1 / (7 • fS) Two Lanes, 12-Bit Serialization 1 / (6 • fS) One Lane, 16-Bit Serialization 1 / (16 • fS) One Lane, 14-Bit Serialization 1 / (14 • fS) One Lane, 12-Bit Serialization 1 / (12 • fS) tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-to-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Set-Up Time l 5 ns tH SCK to CS Set-Up Time l 5 ns tDS SDI Set-Up Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when
Note 2:
All voltage values are with respect to GND with GND and OGND the output code flickers between 00 0000 0000 0000 and 11 1111 1111 shorted (unless otherwise noted). 1111 in 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2265), 40MHz of greater than 100mA below GND or above VDD without latchup. (LTC2264), or 25MHz (LTC2263), 2-lane output mode, ENC+ = single-
Note 4:
When these pin voltages are taken below GND they will be ended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential clamped by internal diodes. When these pin voltages are taken above VDD drive, unless otherwise noted. The supply current and power dissipation they will not be clamped by internal diodes. This product can handle input specifications are totals for the entire chip, not per channel. currents of greater than 100mA below GND without latchup.
Note 10:
Recommended operating conditions.
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2265), 40MHz
Note 11:
The maximum sampling frequency depends on the speed grade (LTC2264), or 25MHz (LTC2263), 2-lane output mode, differential ENC+/ of the part and also which serialization mode is used. The maximum serial ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless data rate is 1000Mbps, so tSER must be greater than or equal to 1ns. otherwise noted. 22654314fb 6 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts