Datasheet TPLD1201 (Texas Instruments) - 8

TPLD1201
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024
www.ti.com
over operating free-air temperature range (unless otherwise noted)
TEST PARAMETER V CONDITIONS CC MIN TYP MAX UNIT
TA = 25℃ VREF = 150mV -10.2 10.2 - 300mV –40°C < TA ≤ 125°C -11 11 TA = 25℃ VREF = 350mV -5 5 - 600mV –40°C < TA ≤ 125°C -5.5 5.5 VREF VREF error 1.71V to 5.5V % TA = 25℃ VREF = 650mV -3.3 3.3 - 1000mV –40°C < TA ≤ 125°C -4.3 4.3 TA = 25℃ VREF = -4 4 1050mV - –40°C < TA ≤ 125°C 1200mV -5 5 ILOAD Output Current 1.71V to 5.5V 500 µA dVOUT/ Output voltage temperature drift 1.71V to 5.5V 550 ppm/ºC dT dVOUT/ Load regulation 1.71V to 5.5V 0.1 1 mV/µA dILOAD (1) Open drain switching performance will be limited by pull-up resistors used
5.6 Supply Current Characteristics
TA = 25°C (unless otherwise noted)
TEST VCC = 1.8V ± 0.09V VCC = 3.3V ± 0.3V VCC = 5V ± 0.5V PARAMETER UNIT CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX Standby
Inputs = static, Outputs = Quiescent ICC open, 3.41 3.66 4.00 µA current IO = 0, OSC powered off
Oscillator
Predivide = 1 3.21 5.24 10.1 OSC0 enabled: Predivide = 2 3.14 5.17 10.1 25kHz Predivide = 4 3.53 5.11 10.1 Quiescent Predivide = 8 3.08 5.28 10.0 ICC µA current Predivide = 1 42.9 56.0 84.9 OSC0 enabled: 2MHz Predivide = 2 35.9 49.0 79.2 Predivide = 4 32.5 45.6 75.5 Predivide = 8 30.7 43.8 73.8
Analog Comparator
External VREF, 24.8 26.2 26.8 Quiescent Discrete analog I IN+ = 0V CC µA current comparator (ACMP) Additional 3.2 4.7 4.7 ACMP
Voltage Reference
Quiescent Voltage reference ICC 16.8 18.3 19.9 µA current (VREF) 8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPLD1201 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data