Datasheet TPLD1201 (Texas Instruments) - 7

TPLD1201 www.ti.com
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024 over operating free-air temperature range (unless otherwise noted)
TEST PARAMETER V CONDITIONS CC MIN TYP MAX UNIT
TA = 25℃ VHYS = 0 mV, -10 10 Gain = 1, Voffset Input offset voltage 1.71V to 5.5V mV VREF= 50mV - –40°C < TA ≤ 125°C -15 15 1200mV VHYS = 0 mV, dVIO/d Gain = 1, Input offset voltage drift –40°C < T 1.71V to 5.5V ±8.5 µV/ºC T A ≤ 125°C VREF= 50mV - 1200mV IB Input bias current 1 µA CID Input capacitance, differential 3 pF CIM Input capacitance, common mode 3 pF Low to High, Low bandwidth 1.5 enabled High to Low Low bandwidth 2.5 Gain = 1, Propagation delay, enabled PROP Vref = 50mV - 1200mV, 1.71V to 5.5V µs response time Overdrive = 50mV Low to High, Low bandwidth 0.25 disabled High to Low Low bandwidth 0.15 disabled
Analog Comparator - Hysteresis
TA = 25℃ 16 21.6 35 VHYS = 25mV -40ºC to 125ºC 15 40 TA = 25℃ 42 50.7 62 VHYS Built-in hysteresis VHYS = 50mV 1.71V to 5.5V mV -40ºC to 125ºC 40 65 TA = 25℃ 170 202 240 VHYS = 200mV -40ºC to 125ºC 165 245
Analog Comparator - Input Gain
Gain = 0.5 1 Rsin Series input resistance Gain = 0.33 1.71V to 5.5V 0.75 MΩ Gain = 0.25 1 Gain = 0.5 -1 1 Gerr Gain error Gain = 0.33 1.71V to 5.5V -1.25 2.75 % Gain = 0.25 -1.5 2.5
Voltage Reference
TA = 25℃ VREF = 150mV -8.5 8.5 - 300mV –40°C < TA ≤ 125°C -9 9 TA = 25℃ VREF = 350mV -3 3 - 600mV –40°C < TA ≤ 125°C -4 4 VREF Internal VREF error 1.71V to 5.5V % TA = 25℃ VREF = 650mV -2.5 2.5 - 1000mV –40°C < TA ≤ 125°C -4 4 TA = 25℃ VREF = -3 3 1050mV - –40°C < TA ≤ 125°C 1200mV -3.7 3.7 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPLD1201 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data