MAX3280E/MAX3281E/ ±15kV ESD-Protected 52Mbps, 3V to 5.5V, MAX3283E/MAX3284E SOT23 RS-485/RS-422 True Fail-Safe Receivers Absolute Maximum Ratings (All Voltages Referenced to GND) Continuous Power Dissipation (TA = +70°C) Supply Voltage (VCC) ..-0.3V to +6V 5-Pin SOT23 (derate 3.9mW/°C above +70°C) ...312.60mW Control Input Voltage (EN, EN) ...-0.3V to +6V 6-Pin SOT23 (derate 8.7mW/°C above +70°C) ..696mW VL Input Voltage ..-0.3V to +6V Operating Temperature Range Receiver Input Voltage (A, B) ...-7.5V to +12.5V MAX328_EA__ ... -40°C to +125°C Receiver Output Voltage (RO) ... -0.3V to (VCC + 0.3V) Storage Temperature Range .. -65°C to +150°C Receiver Output Voltage Junction Temperature ..+150°C (RO) (MAX3284E) ...-0.3V to (VL + 0.3V) Lead Temperature (soldering, 10s) ...+300°C Receiver Output Short-Circuit Current ..Continuous Soldering Temperature (reflow) ...+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package InformationSOT23-5PACKAGE CODEU5+2, U5+2A Outline Number 21-0057 Land Pattern Number 90-0174Thermal Resistance, Single-Layer Board: Junction to Ambient (θJA) 324.30°C/W Junction to Case (θJC) 82°C/W Thermal Resistance, Multi-Layer Board: Junction to Ambient (θJA) 255.90°C/W Junction to Case (θJC) 81°C/W SOT23-6PACKAGE CODEU6+1 Outline Number 21-0058 Land Pattern Number 90-0175Thermal Resistance, Single-Layer Board: Junction to Ambient (θJA) N/A Junction to Case (θJC) 80°C/W Thermal Resistance, Multi-Layer Board: Junction to Ambient (θJA) 115°C/W Junction to Case (θJC) 80°C/W For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . www.maximintegrated.com Maxim Integrated │ 2