Datasheet INN5375F, INN5376F, INN5377F, INN5396F, INN5475F, INN5476F, INN5477F, INN5496F (Power Integrations) - 7

InnoSwitch5-Pro Frequency Soft-Start Open SR Protection
At start-up the primary control er is limited to a maximum switching In order to protect against an open SYNCHRONOUS RECTIFIER frequency of f and 75% of the maximum programmed current limit DRIVE pin system fault the secondary control er has a protection SW at the switch-request frequency of 100 kHz. mode to ensure the SYNCHRONOUS RECTIFIER DRIVE pin is connected to an external FET. If the external capacitance on the After hand-shake is completed the secondary control er linearly SYNCHRONOUS RECTIFIER DRIVE pin is below ~200 pF, the device ramps up the switching frequency from f to f over the SW SREQ will assume the SYNCHRONOUS RECTIFIER DRIVE pin is “open” and ~10 ms time period. there is no FET to drive. If the pin capacitance detected is above In the event of a short-circuit or overload at start-up, the device will ~200 pF, the control er will assume an SR FET is connected. move directly into CC (constant-current) mode. The device will go In the event the SYNCHRONOUS RECTIFIER DRIVE pin is detected to into auto-restart (AR), if the output voltage does not rise above the be open, the secondary control er will stop requesting pulses from 3.6 V before the expiration of the soft-start timer after handshake the primary to initiate auto-restart. has occurred. If the SYNCHRONOUS RECTIFIER DRIVE pin is tied to ground at If the output voltage reaches regulation within the soft-start time start-up, the SR drive function is disabled and the open SYNCHRONOUS period, the frequency ramp is immediately aborted and the secondary RECTIFIER DRIVE pin protection mode is also disabled. control er is permitted to go full frequency. This will al ow the control er to maintain regulation in the event of a sudden transient
Dynamically Programmable ZVS Operation in DCM mode
loading soon after regulation is achieved. The frequency ramp will
using Synchronous Rectifier
only be aborted if quasi-resonant-detection programming has already In order to improve the conversion efficiency and eliminate switching occurred. losses, the InnoSwitch5-Pro IC features a means of achieving zero voltage switching of the primary switch by enabling the synchronous
Maximum Secondary Inhibit Period
rectifier for short period before sending the switching request in DCM Secondary requests to initiate primary switching are inhibited to mode of operation. During this time magnetizing current is charged maintain operation below maximum frequency and ensure minimum in negative direction at the rate determined by the reflected output off-time. Besides these constraints, secondary-cycle requests are voltage on the primary. At the end of SR conduction time, the also inhibited during the “ON” time cycle of the primary switch (time magnetizing energy will start discharging the drain node capacitance between the cycle request and detection of FORWARD pin falling on the primary switch to force the voltage across the primary power edge). The maximum time-out in the event that a FORWARD pin switch to zero before every conduction cycle. This mode of operation falling edge is not detected after a cycle requested is ~30 ms. is available only in the Discontinuous Conduction Mode and the
SR Disable Protection
feature gets disabled automatical y when there is a CCM switching In each cycle SR is only engaged if a set cycle was requested by the request. Power converter can be enforced to operate in DCM only secondary control er and the negative edge is detected on the mode by sending I2C command. Enabling SR-ZVS mode benefits the FORWARD pin. In the event that the voltage on the ISENSE pin SRFET as well by limiting the peak voltage across the SRFET when exceeds approximately 3 times the CC threshold, the SR FET drive is primary switch turns ON. See Figure 7. disabled until the surge current has diminished to nominal levels. Rather than detecting the magnetizing ring peak on the primary-side, In SRZVS mode of operation, it is recommended to write 0x0E09 into the val ey voltage of the FORWARD pin voltage as it fal s below the the command register address 0x38 (with parity) to disable SR gate output voltage is used to initiate the SR-ZVS operation. The details of drive under any circumstances of primary switching without any cycle I2C programming commands for this mode are provided in the request from the secondary controller or cross conduction detection command register section of the data sheet. event. The detection is based on the signal on FORWARD pin and if the signal FORWARD pin has rings going below ground (<0 V, during SRZVS mode of operation uses output energy to achieve the DCM mode of operation), this can result in SR gate drive being zero-voltage switching of the primary power switch. It is beneficial disabled in the subsequent switching cycles. It is recommended to when used at high input line condition and higher load conditions with improve the FORWARD pin signal to not have any DCV ringing going sufficient reflected output voltage to charge the magnetizing current below ground during normal operation to avoid SR gate drive disable in negative direction in short period. protection to trigger. In such designs, bit[2:0] of the command above In SR-ZVS mode, a TVS diode in the primary clamp circuit is required can be incremented in steps of 1b’1 to avoid this protection feature to to limit the peak drain voltage of InnoSwitch5-Pro primary switch trigger under normal operation conditions. during abnormal transient events such as ESD and EFT. When the SR gate drive is disabled due to this protection feature,
Intelligent Quasi-Resonant Mode Switching
Quasi-resonant switching also gets disable and both SR gate drive In order to improve conversion efficiency and reduce switching losses, and Quasi-resonant switching get reinstated automatical y once the the lnnoSwitch5-Pro IC features a means to force switching when the fault condition is cleared. If this protection feature interferes with voltage across the primary switch is near its minimum voltage when normal operation at certain conditions, and of not desirable, it can be the converter operates in discontinuous conduction mode (DCM). disabled by writing 0x0201 into 0x38 (with parity) command register. This mode of operation is automatical y engaged in DCM and disabled once the converter moves to continuous conduction mode (CCM). In non-SRZVS mode of opeation, it is recommended to write 0x0A09 See Figure 8. into the command register address 0x38 (with parity) to enable this protection feature. To disable the protection feature write 0x0201 Rather than detecting the magnetizing ring val ey on the primary - into the same command register. side, the peak voltage of the FORWARD pin voltage as it rises above
SR Static Pull-Down
the output voltage level is used to gate secondary requests to initiate To ensure that the SR gate is held low when the secondary is not in the switch “ON” cycle in the primary control er. control, the SYNCHRONOUS RECTIFIER DRIVE pin has internal The secondary control er detects when the control er enters in nominal y “ON” device to pull the pin low and reduce any voltage on discontinuous-mode and opens secondary cycle request windows the SR gate due to capacitive coupling from the FORWARD pin. corresponding to minimum switching voltage across the primary power switch.
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Rev. C 01/24 www.power.com