Datasheet SiC967 (Vishay) - 7

SiC967
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Control Scheme Operating Modes
SiC967 employs a voltage - mode COT control mechanism SiC967 can operate in forced continuous conduction mode in conjunction with adaptive zero current detection which or power save mode. To improve efficiency at light-loads, allows for power saving in discontinuous conduction mode SiC967 provides a set of innovative implementations to (DCM). The switching frequency, fSW, is set by an external eliminate LS re-circulating current and switching losses. The resistor Rfsw connected from fsw pin to ground. The SiC967 internal zero crossing detector (ZCD) monitors PHASE node operates between 200 kHz to 2 MHz depending on VIN and voltage to determine when inductor current starts to flow VOUT conditions. negatively. In power saving mode, as soon as inductor valley current crosses zero, the device first deploys diode V R OUT = ----------------------- emulation mode by turning off the LS FET. If load further fsw -12 f  190  10 decreases, switching frequency is reduced proportional to sw Note, that there is no V the load condition to save switching losses while keeping IN dependency on fSW as long as VIN and V output ripple within tolerance. CIN are connected to the same supply. SiC967 employs an advanced voltage - mode COT control To improve the converter efficiency, the user can choose to mechanism. disable the internal VDRV regulator by picking either mode 3 During steady-state operation, feedback voltage (V or mode 4 and connecting a 5 V supply to the VDRV pin. This FB) is compared with internal reference (0.8 V typ.) and the reduces power dissipation in the SiC967 by eliminating the amplified error signal (V VDRV linear regulator losses. COMP) is generated at the internal comp node. An internally generated ramp signal and VCOMP The mode pin supports several modes of operation as feed into a comparator. Once VRAMP crosses VCOMP, an shown in table 1. An internal current source is used to set on-time pulse is generated for a fixed time. During the the voltage on this pin using an external resistor: on-time pulse, the high side MOSFET will be turned on. Once the on-time pulse expires, the low side MOSFET will be turned on after a dead time period. The low side MOSFET
TABLE 1 - OPERATION MODES
will stay on for a minimum duration equal to the minimum
POWER SAVE INTERNAL V MODE RANGE (k ) DRV
off-time (t
MODE REGULATOR
OFF_MIN.) and remains on until VRAMP crosses V 1 0 to 100 Enabled On COMP. The cycle is then repeated. 2 298 to 304 Disabled On Fig. 5 illustrates the operation as described above. 3 494 to 504 Disabled Off (1) 4 900 to 1100 Enabled Off (1)
Note
VRAMP (1) Connect a 5 V (± 5 %) supply to the VDRV pin The mode pin is not latched to any state and can be V changed on the fly. COMP PWM Fixed on-time
Fig. 6 - Operational Principle
S23-0680-Rev. C, 28-Aug-2023
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