Datasheet SiC967 (Vishay) - 8

SiC967
www.vishay.com Vishay Siliconix
OUTPUT MONITORING AND PROTECTION FEATURES Output Over-Current Protection (OCP) Enable
SiC967 has cycle by cycle current limiting. The inductor The SiC967 has an enable pin to turn the part on and off. valley current is monitored during LS FET turn-on period Driving this pin high enables the device, while grounding it through RDS(on) sensing. After a pre-defined blanking time, turns it off. the valley current is compared with an internal threshold. If The SiC967 enable has a weak pull down to prevent monitored current is higher than threshold, high side unwanted turn on due to a floating GPIO. MOSFET is kept off until the inductor current falls below OCP threshold. There are no sequencing requirements with respect to other input / output supplies. OCP is enabled immediately after VDD passes UVLO rising threshold.
Pre-Bias Start-Up
There are 3 settings for the valley current OCP namely 50 %, In case of pre-bias startup, if the sensed voltage on FB is 75 % and 100 %. The selection can be chosen by higher than the internal soft-start ramp value, control logic connecting the ILIMIT pin either to VDD, float or GND. prevents HS and LS FET from switching to avoid negative Connecting to VDD will select 100 % of the preset valley output voltage spike and excessive current sinking through current OCP corresponding to the SiC967 being used. If the LS FET. pin is floating, the valley current OCP is 75 %. Connecting to GND, the valley current OCP is 50 %. OCPthreshold Iload Iinductor GH
Fig. 7 - Over-Current Protection Illustration Output Undervoltage Protection (UVP) Fig. 8 - Pre-Bias Start-Up
UVP is implemented by monitoring output through VFB pin. If the voltage level at V
Power Good
FB goes below 0.16 V (VOUT is 20 % of VOUT set point) for more than 25 μs a UVP event is SiC967’s power good is an open-drain output. Pull PGOOD recognized and both HS and LS MOSFETs are turned off. pin high up to 5 V through a 10K resistor to use this signal. After a time-out period equal to 20 soft start cycles, the IC Power good window is shown in the Fig. 8. If voltage level attempts to re-start by going through a soft start cycle. If the on FB pin is out of this window, PG signal is de-asserted by fault condition still exists, the above cycle will be repeated. pulling down to GND. To prevent false triggering during UVP is only active after the completion of soft-start transient events, PGOOD has a 25 μs blanking time. sequence.
Output Over Voltage Protection (OVP)
For OVP implementation, output is monitored through FB VFB_Rising_Vth_OV (typ. = 0.96 V) pin. After soft start, if the voltage level at FB is above 0.96 V VFB_Falling_Vth_OV (typ. = 0.91 V) (typ.) (V V (0.8 V) OUT is 120 % of VOUT set point), OVP is triggered with ref both the HS and LS MOSFETs turned off. Normal operation VFB_Falling_Vth_UV V (typ. = 0.72 V) VFB_Rising_Vth_UV is resumed once FB voltage drops back to 0.96 V. FB (typ. = 0.77 V) OVP is active immediately after VDD passes UVLO level.
Over Temperature Protection (OTP)
Pull-high PG SiC967 has internal thermal monitor block that turns off both HS and LS FETs when junction temperature is above 150 °C (typ). A hysteresis of 35 °C is implemented, so when junction Pull-low temperature drops below 115 °C, the device restarts by
Fig. 9 - PGOOD Window and Timing Diagram
initiating soft-start sequence again.
Sequencing of Input / Output Supplies
SiC967 has no sequencing requirements on any of its input / output (VIN, VDRV, VDD, VCIN, EN) supplies or enables. S23-0680-Rev. C, 28-Aug-2023
8
Document Number: 76444 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000