Datasheet AP7179D (Diodes) - 4

AP7179D Pin Descriptions Pin Number Pin Name Function
LDO output pin. Connect a 47μF or larger ceramic capacitor (22μF or greater of capacitance) is 1, 19, 20 OUT required for stability and the output capacitor as close to the device as possible to minimize the impedance between OUT pin to load. Output voltage sense input pin. Connect this pin to OUT only if using the programmed output voltage 2 SNS function (set the output voltage via PCB layout). If the OUT voltage is set by external resistor, leave this pin floating. Feedback voltage pin connected to the error amplifier. This pin is used to set the output voltage by an 3 FB external resistive divider. The typically reference voltage is 0.8V. Output voltage power good indicator pin. Active-high with open-drain outputs when output voltage 4 PG reaches 88% of the target. The pin is pulled to ground when the output voltage is lower than threshold, EN pulled down, OCP and OTP. 50mV, 100mV, Output voltage setting pins. Connect these pins to ground or leave floating. Connecting theses pins 5, 6, 7, 9, 10, 11 200mV, 400mV, to ground increases the output voltage; multiple pins can be simultaneously connected to GND to 800mV, 1.6V select the desired output voltage. Leaves these pins floating (open) when not in use. Ground pin. These pins must be connected to ground. The exposed pad solders to ground with large 8,18, 21 (Exposed Pad) GND PCB to enhance the power dissipation. 12 NC No internal connection. Leave this pin floating doesn’t affect the chip functionality. Noise-reduction and soft-start pin. This pin Connect an external capacitor to ground reduce the 13 NR/SS reference voltage noise and slow down the output voltage rise as a soft-start. A 10nF or larger capacitor connects between NR/SS to ground for low noise applications. Enable pin. Connecting this pin to logic high enables the device or connecting this pin to logic low 14 EN disables the device. If enable functionality is required; connecting high with EN pin after VIN voltage is established. Connecting EN pin to VIN always, if the enable functionality is not required Input supply voltage pin. Connecting a 47μF or large ceramic capacitor from IN to ground as close as 15, 16, 17 IN possible to get better noise rejection performance.
Functional Block Diagram
IN OUT Charge Gate Active Pump Driver Discharge Current Limit EN PG OTP Enable Logic 0.88 x VREF UVLO Error 250k Amp SNS VREF 2R I FB NR/SS 32R 16R 8R 4R 2R 1R NR/SS 50mV 100mV 200mV 400mV 800mV 1.6V AP7179D 4 of 20 January 2023 Document number: DS42129 Rev. 2 - 2
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