Datasheet MTP3N60E (ON Semiconductor) - 8
| Hersteller | ON Semiconductor |
| Beschreibung | TMOS E−FET High Energy Power FET N−Channel Enhancement−Mode Silicon Gate |
| Seiten / Seite | 9 / 8 — MTP3N60E. Figure 16. Capacitance Variation. Figure 17. Gate Charge … |
| Dateiformat / Größe | PDF / 292 Kb |
| Dokumentensprache | Englisch |
MTP3N60E. Figure 16. Capacitance Variation. Figure 17. Gate Charge versus. Gate−To−Source Voltage
Modelllinie für dieses Datenblatt
MTP3N60E
Textversion des Dokuments
MTP3N60E
1600 16 T TS) J = 25°C V 1400 T DS = 100 V J = 25°C I V D = 3 A GS = 0 V 1200 12 250 V TAGE (VOL 420 V 1000 C ANCE (pF) iss 800 Crss 8 ACIT 600 O−SOURCE VOL C, CAP 400 4 TE−T VDS = 0 V 200 C , GA oss GSV 0 0 10 5 0 5 10 15 20 25 0 5 10 15 20 25 30 35 4 VGS VDS Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 16. Capacitance Variation Figure 17. Gate Charge versus Gate−To−Source Voltage
+18 V VDD 1 mA SAME 10 V 100 k DEVICE TYPE Vin 15 V AS DUT 2N3904 0.1 μF 2N3904 100 k FERRITE 47 k BEAD 100 DUT Vin = 15 Vpk; PULSE WIDTH ≤ 100 μs, DUTY CYCLE ≤ 10%
Figure 18. Gate Charge Test Circuit http://onsemi.com 7
1600 16 T TS) J = 25°C V 1400 T DS = 100 V J = 25°C I V D = 3 A GS = 0 V 1200 12 250 V TAGE (VOL 420 V 1000 C ANCE (pF) iss 800 Crss 8 ACIT 600 O−SOURCE VOL C, CAP 400 4 TE−T VDS = 0 V 200 C , GA oss GSV 0 0 10 5 0 5 10 15 20 25 0 5 10 15 20 25 30 35 4 VGS VDS Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 16. Capacitance Variation Figure 17. Gate Charge versus Gate−To−Source Voltage
+18 V VDD 1 mA SAME 10 V 100 k DEVICE TYPE Vin 15 V AS DUT 2N3904 0.1 μF 2N3904 100 k FERRITE 47 k BEAD 100 DUT Vin = 15 Vpk; PULSE WIDTH ≤ 100 μs, DUTY CYCLE ≤ 10%
Figure 18. Gate Charge Test Circuit http://onsemi.com 7