Datasheet MTP3N60E (ON Semiconductor) - 7
| Hersteller | ON Semiconductor |
| Beschreibung | TMOS E−FET High Energy Power FET N−Channel Enhancement−Mode Silicon Gate |
| Seiten / Seite | 9 / 7 — MTP3N60E. Figure 13. Commutating Safe Operating Area. Test Circuit. … |
| Dateiformat / Größe | PDF / 292 Kb |
| Dokumentensprache | Englisch |
MTP3N60E. Figure 13. Commutating Safe Operating Area. Test Circuit. Figure 10. Thermal Response
Modelllinie für dieses Datenblatt
MTP3N60E
Textversion des Dokuments
RGS DUT
MTP3N60E
− 1 4 VR D = 0.5 0.5 + I + FM IS Li ANCE 0.3 + VDS 0.2 3 RESIST 0.2 20 V (AMPS) 0.1 − V 0.1 GSP(pk) RθJC(t) = r(t) RθJC 0.05 2 THERMAL RθJC = 1.67°C/W MAX V 0.05 R D CUR = 80% OF RA VES APPL TED VDS Y FOR POWER 0.02 di/dt , NORMALIZED EFFECTIVE ≤ 60 A/μs VdsL = Vf + Li ⋅ dls/dt PULSE TRAIN SHOWN t1 r(t) 0.03 READ TIME AT t1 , DRAIN CURRENT t2 I D 1 TRANSIENT 0.02 0.01
Figure 13. Commutating Safe Operating Area
TJ(pk) − TC = P(pk) RθJC(t) DUTY CYCLE, D = t1/t2 SINGLE PULSE
Test Circuit
0.01 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1 0 0 200 400 600 800 t, TIME (ms) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) V(BR)DSS
Figure 10. Thermal Response Figure 12. Commutating Safe Operating Area (CSOA)
Vds(t)
COMMUTATING SAFE OPERATING AREA (CSOA)
IO 15 V The Commutating Safe Operating Area (CSOA) of Figure V 12 defines the limits of safe GS L operation for commutated 0 I source-drain current versus re-applied drain voltage when D(t) V I DS C FM dl 4700 μF the source-drain diode has undergone forward bias. The S/dt 90% ID curve shows the limitations of IFM and peak V 250 V R for a given I commutation speed. It is applicable when waveforms S t V rr DD similar to those of Figure 11 are present. Full or half-bridge 10% VDD PWM DC motor controllers are common applications ton I t requiring CSOA data. RM tP t, (TIME) The time interval t 0.25 I R RM frr is GS the speed of the commutation t cycle. frr 50 Ω Device stresses increase with commutation speed, V ǒ V(BR)DSS Ǔ WDSR + ǒ1 LI 2 O2Ǔ V DS(pk) (BR)DSS–VDD so tfrr is specified with a minimum value. Faster
Figure 14. Unclamped Inductive Switching
commutation speeds require an appropriate derating of IFM,
Figure 15. Unclamped Inductive Switching
VR peak VR
T
or both. Ultimately,
est Circuit
tfrr is limited primarily by device,
Waveforms
package, and circuit impedances. Maximum device stress VDS occurs during t V rr as the diode goes from conduction to V dsL f reverse blocking. VDS(pk) is the peak drain−to−source voltage that the MAX. CSOA device must sustain during commutation; IFM is the STRESS AREA maximum forward source-drain diode current just prior to the onset of commutation.
Figure 11. Commutating Waveforms
VR is specified at 80% of V(BR)DSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances, Li in Motorola’s test circuit are assumed to be practical minimums.
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MTP3N60E
− 1 4 VR D = 0.5 0.5 + I + FM IS Li ANCE 0.3 + VDS 0.2 3 RESIST 0.2 20 V (AMPS) 0.1 − V 0.1 GSP(pk) RθJC(t) = r(t) RθJC 0.05 2 THERMAL RθJC = 1.67°C/W MAX V 0.05 R D CUR = 80% OF RA VES APPL TED VDS Y FOR POWER 0.02 di/dt , NORMALIZED EFFECTIVE ≤ 60 A/μs VdsL = Vf + Li ⋅ dls/dt PULSE TRAIN SHOWN t1 r(t) 0.03 READ TIME AT t1 , DRAIN CURRENT t2 I D 1 TRANSIENT 0.02 0.01
Figure 13. Commutating Safe Operating Area
TJ(pk) − TC = P(pk) RθJC(t) DUTY CYCLE, D = t1/t2 SINGLE PULSE
Test Circuit
0.01 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1 0 0 200 400 600 800 t, TIME (ms) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) V(BR)DSS
Figure 10. Thermal Response Figure 12. Commutating Safe Operating Area (CSOA)
Vds(t)
COMMUTATING SAFE OPERATING AREA (CSOA)
IO 15 V The Commutating Safe Operating Area (CSOA) of Figure V 12 defines the limits of safe GS L operation for commutated 0 I source-drain current versus re-applied drain voltage when D(t) V I DS C FM dl 4700 μF the source-drain diode has undergone forward bias. The S/dt 90% ID curve shows the limitations of IFM and peak V 250 V R for a given I commutation speed. It is applicable when waveforms S t V rr DD similar to those of Figure 11 are present. Full or half-bridge 10% VDD PWM DC motor controllers are common applications ton I t requiring CSOA data. RM tP t, (TIME) The time interval t 0.25 I R RM frr is GS the speed of the commutation t cycle. frr 50 Ω Device stresses increase with commutation speed, V ǒ V(BR)DSS Ǔ WDSR + ǒ1 LI 2 O2Ǔ V DS(pk) (BR)DSS–VDD so tfrr is specified with a minimum value. Faster
Figure 14. Unclamped Inductive Switching
commutation speeds require an appropriate derating of IFM,
Figure 15. Unclamped Inductive Switching
VR peak VR
T
or both. Ultimately,
est Circuit
tfrr is limited primarily by device,
Waveforms
package, and circuit impedances. Maximum device stress VDS occurs during t V rr as the diode goes from conduction to V dsL f reverse blocking. VDS(pk) is the peak drain−to−source voltage that the MAX. CSOA device must sustain during commutation; IFM is the STRESS AREA maximum forward source-drain diode current just prior to the onset of commutation.
Figure 11. Commutating Waveforms
VR is specified at 80% of V(BR)DSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances, Li in Motorola’s test circuit are assumed to be practical minimums.
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