IRLB8743PbF Driver Gate Drive P.W. D.U.T Period D = P.W. Period + V * Circuit Layout Considerations GS=10V • Low Stray Inductance • Ground Plane - • Low Leakage Inductance D.U.T. I Current Transformer SD Waveform + Reverse Recovery Body Diode Forward Current Current - + - di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD • dv/dt controlled by R V G DD Re-Applied RG + Voltage • Driver same type as D.U.T. Body Diode Forward Drop • ISD controlled by Duty Factor "D" - Inductor Curent • D.U.T. - Device Under Test Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Current Regulator Same Type as D.U.T. Id Vds 50KΩ Vgs .2µF 12V .3µF +V D.U.T. DS - Vgs(th) VGS 3mA I I Qgodr Qgd Qgs2 Qgs1 G D Current Sampling Resistors Fig 16. Gate Charge Test Circuit Fig 17. Gate Charge Waveform www.irf.com 7