Datasheet ADG1519 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 3.8 Ω On-Resistance, SPDT Switch |
| Seiten / Seite | 15 / 6 — ADG1519. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. Figure 2. Pin … |
| Dateiformat / Größe | PDF / 673 Kb |
| Dokumentensprache | Englisch |
ADG1519. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. Figure 2. Pin Configuration. Table 5. Pin Function Descriptions. Pin No
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 6 Data Sheet
ADG1519 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 D Drain Terminal. The D pin can be an input or output. 2 SA Source Terminal. The SA pin can be an input or output. 3 GND Ground (0 V) Reference. 4 VDD Most Positive Power Supply Potential. Decouple the VDD pin using a 0.1 μF capacitor to GND. 5 EN Active High Digital Input. When the EN pin is low, the device is disabled, and the SA, SB, and D terminals are high impedance. When the EN pin is high, the IN logic input determines which switch is turned on. 6 IN Logic Control Input. 7 VSS Most Negative Power Supply Potential. Decouple the VSS pin using a 0.1 µF capacitor to GND. 8 SB Source Terminal. The SB pin can be an input or output. 0 EPAD Exposed Pad. Exposed pad tied to substrate, VSS.
Table 6. Truth Table EN IN D
0 X1 High impedance 1 0 SA 1 1 SB 1 X means don't care.
analog.com Rev. 0 | 6 of 15
Document Outline Features Applications General Description Functional Block Diagram Product Highlights Specifications Dual Supply Continuous Current Per Channel, Sx or D Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology IDD ISS VD and VS RON RFLAT ON IS Off ID Off ID and IS On VINL VINH IINL and IINH CS Off CD Off CD and CS On CIN tON EN tOFF EN tTRANSITION TD Charge Injection Off Isolation Crosstalk Bandwidth Insertion Loss THD + N THD AC PSRR Applications Information Power Amplifier Gate Drive Power Supply Rails Power Supply Recommendations Outline Dimensions Ordering Guide Evaluation Boards
ADG1519 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 D Drain Terminal. The D pin can be an input or output. 2 SA Source Terminal. The SA pin can be an input or output. 3 GND Ground (0 V) Reference. 4 VDD Most Positive Power Supply Potential. Decouple the VDD pin using a 0.1 μF capacitor to GND. 5 EN Active High Digital Input. When the EN pin is low, the device is disabled, and the SA, SB, and D terminals are high impedance. When the EN pin is high, the IN logic input determines which switch is turned on. 6 IN Logic Control Input. 7 VSS Most Negative Power Supply Potential. Decouple the VSS pin using a 0.1 µF capacitor to GND. 8 SB Source Terminal. The SB pin can be an input or output. 0 EPAD Exposed Pad. Exposed pad tied to substrate, VSS.
Table 6. Truth Table EN IN D
0 X1 High impedance 1 0 SA 1 1 SB 1 X means don't care.
analog.com Rev. 0 | 6 of 15
Document Outline Features Applications General Description Functional Block Diagram Product Highlights Specifications Dual Supply Continuous Current Per Channel, Sx or D Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology IDD ISS VD and VS RON RFLAT ON IS Off ID Off ID and IS On VINL VINH IINL and IINH CS Off CD Off CD and CS On CIN tON EN tOFF EN tTRANSITION TD Charge Injection Off Isolation Crosstalk Bandwidth Insertion Loss THD + N THD AC PSRR Applications Information Power Amplifier Gate Drive Power Supply Rails Power Supply Recommendations Outline Dimensions Ordering Guide Evaluation Boards