Datasheet RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 (Renesas) - 4

HerstellerRenesas
BeschreibungLarge 3V Output Swing, 5kV EFT, 16.5kV ESD, RS-485 Transceivers
Seiten / Seite34 / 4 — RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 …
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DokumentenspracheEnglisch

RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet. 2.2. Pin Descriptions. 8 Ld. 10 Ld. 14 Ld. Pin. SOIC. MSOP

RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet 2.2 Pin Descriptions 8 Ld 10 Ld 14 Ld Pin SOIC MSOP

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RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet 2.2 Pin Descriptions 8 Ld 10 Ld 14 Ld Pin SOIC MSOP SOIC Name Function
1 1 2 RO Receiver output: If A-B ≥ -50mV, RO is high; If A-B ≤ -200mV, RO is low. RO is fail-safe High if A and B are unconnected (open) or shorted. 2 2 3 RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. 3 3 4 DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. 4 4 5 DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. 5 5 6, 7 GND Ground connection. 6 – – A/Y Non-inverting receiver input and non-inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. 7 – – B/Z Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. – 6 9 Y Non-inverting driver output. – 7 10 Z Inverting driver output. – 8 11 B Inverting receiver input. – 9 12 A Non-inverting receiver input. 8 10 – VCC System power supply input (4.5V to 5.5V). – – 1, 8, 13 NC No connection. R15DS0005EU0102 Rev.1.02 Page 4 Aug 19, 2021 Document Outline Features Applications Contents 1. Overview 1.1 Typical Operating Circuit 2. Pin Information 2.1 Pin Assignments 2.2 Pin Descriptions 3. Specifications 3.1 Absolute Maximum Ratings 3.2 Recommended Operating Conditions 3.3 Thermal Information 3.4 Electrical Specifications 4. Test Circuits and Waveforms 5. Typical Performance Curves 6. Device Description 6.1 Overview 6.2 Functional Block Diagram 6.3 Operating Modes 6.3.1 Driver Operation 6.3.2 Receiver Operation 6.4 Device Features 6.4.1 Large Output Signal Swing 6.4.2 Driver Overload Protection 6.4.3 Full-Failsafe Receiver 6.4.4 Low Current Shutdown Mode 6.4.5 Hot Plug Function 6.4.6 High EFT Immunity 6.4.7 High ESD Protection 7. Application Information 7.1 Network Design 7.1.1 Cable Type 7.1.2 Cable Length vs Data Rate 7.1.3 Topologies and Stub Lengths 7.1.4 Minimum Distance between Nodes 7.1.5 Failsafe Biasing Termination 7.2 Transient Protection 7.3 Layout Guidelines 7.3.1 Layout Example 8. Package Outline Drawings 9. Ordering Information 10. Revision History