Datasheet AD548 (Analog Devices) - 7

AD548
TPC 19a. Unity Gain Follower TPC 19b. Unity Gain Follower TPC 19c. Unity Gain Follower Pulse Response (Large Signal) Pulse Response (Small Signal) TPC 20a. Utility Gain Inverter TPC 20b. Utility Gain Inverter TPC 20c. Unity Gain Inverter Pulse Response (Large Signal) Pulse Response (Small Signal)
APPLICATION NOTES
The AD548 is a JFET-input op amp with a guaranteed maxi- mum IB of less than 10 pA, and offset and drift laser-trimmed to 0.5 mV and 5 µV/°C, respectively (AD548B). AC specs include 1 MHz bandwidth, 1.8 V/µs typical slew rate and 8 µs settling time for a 20 V step to ± 0.01%—all at a supply current less than 200 µA. To capitalize on the device’s performance, a number of error sources should be considered. The minimal power drain and low offset drift of the AD548 reduce self-heating or “warm-up” effects on input offset voltage, making the AD548 ideal for on/off battery-powered applica- Figure 1. Offset Null Configuration tions. The power dissipation due to the AD548’s 200 µA supply current has a negligible effect on input current, but heavy out-
LAYOUT
put loading will raise the chip temperature. Since a JFET’s To take full advantage of the AD548’s 10 pA max input current, input current doubles for every 10°C rise in chip temperature, parasitic leakages must be kept below an acceptable level. The this can be a noticeable effect. practical limit of the resistance of epoxy or phenolic circuit board material is between 1 × 1012 Ω and 3 × 1012 Ω. This can The amplifier is designed to be functional with power supply result in an additional leakage of 5 pA between an input of 0 V voltages as low as ± 4.5 V. It will exhibit a higher input offset and a –15 V supply line. Teflon® or a similar low leakage mate- voltage than at the rated supply voltage of ± 15 V, due to power rial (with a resistance exceeding 1017 Ω) should be used to supply rejection effects. The common-mode range of the AD548 isolate high impedance input lines from adjacent lines carrying extends from 3 V more positive than the negative supply to 1 V high voltages. The insulator should be kept clean, since con- more negative than the positive supply. Designed to cleanly taminants will degrade the surface resistance. drive up to 10 kΩ and 100 pF loads, the AD548 will drive a 2 kΩ load with reduced open-loop gain. A metal guard completely surrounding the high impedance nodes and driven by a voltage near the common-mode input potential
OFFSET NULLING
can also be used to reduce some parasitic leakages. The guarding Unlike bipolar input amplifiers, zeroing the input offset voltage pattern in Figure 2 will reduce parasitic leakage due to finite of a BiFET op amp will not minimize offset drift. Using balance board surface resistance; but it will not compensate for a low Pins 1 and 5 to adjust the input offset voltage as shown in volume resistivity board. Figure 1 will induce an added drift of 0.24 µV/°C per 100 µV of nulled offset. The low initial offset (0.5 mV) of the AD548B results in only 0.6 µV/°C of additional drift. Teflon is a registered trademark of DuPont. REV. D –7–