Datasheet AD548 (Analog Devices) - 8

AD548
Figure 2. Board Layout for Guarding Inputs
INPUT PROTECTION
The AD548 is guaranteed to withstand input voltages equal to Figure 4. AD548 Used as DAC Output Amplifier the power supply potential. Exceeding the negative supply volt- That is: age on either input will forward bias the substrate junction of the chip. The induced current may destroy the amplifier due to   V excess heat. OS Output = VOS Input 1+ RFB R   O Input protection is required in applications such as a flame R detector in a gas chromatograph, where a very high potential FB is the feedback resistor for the op amp, which is internal to the DAC. R may be applied to the input terminals during a sensor fault O is the DAC’s R-2R ladder output resistance. The value of R condition. Figure 3 shows a simple current limiting scheme that O is code dependent. This has the effect of changing the offset error voltage at the amplifier’s output. An output can be used. RPROTECT should be chosen such that the maxi- amplifier with a sub millivolt input offset voltage is needed to mum overload current is 1.0 mA (l00 kΩ for a 100 V overload, preserve the linearity of the DAC’s transfer function. for example). The AD548 in this configuration provides a 700 kHz small Exceeding the negative common-mode range on either input signal bandwidth and 1.8 V/µs typical slew rate. The 33 pF terminal causes a phase reversal at the output, forcing the capacitor across the feedback resistor optimizes the circuit’s amplifier output to the corresponding high or low state. Exceed- response. The oscilloscope charts in Figures 5 and 6 show small ing the negative common-mode on both inputs simultaneously and large signal outputs of the circuit in Figure 4. Upper traces forces the output high. Exceeding the positive common-mode show the input signal V range on a single input does not cause a phase reversal, but if IN. Lower traces are the resulting output voltage with the DAC’s digital input set to all 1s. The AD548 both inputs exceed the limit the output will be forced high. In settles to ± 0.01% for a 20 V input step in 14 µs. all cases, normal amplifier operation is resumed when input voltages are brought back within the common-mode range.
5V 20V 5µS 100 90 10 0%
Figure 5. Response to ±20 V p-p Reference Square Wave Figure 3. Input Protection of IV Converter
50mV 200mV 2µS 100 D/A CONVERTER OUTPUT BUFFER 90
The circuit in Figure 4 shows the AD548 and AD7545 12-bit CMOS D/A converter in a unipolar binary configuration. VOUT will be equal to VREF attenuated by a factor depending on the digital word. VREF sets the full scale. Overall gain is trimmed by adjusting RIN. The AD548’s low input offset voltage, low drift,
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and clean dynamics make it an attractive low power output buffer.
0%
The input offset voltage of the AD548 output amplifier results in an output error voltage. This error voltage equals the input Figure 6. Response to ±100 mV p-p Reference Square Wave offset voltage of the op amp times the noise gain of the amplifier. –8– REV. D