Datasheet LM25149-Q1 (Texas Instruments) - 8

LM25149-Q1
SNVSBV6 – DECEMBER 2020
www.ti.com
TJ = –40°C to +150°C, VIN = 8 V to 18 V. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRT RT pin regulation voltage 10 kΩ < RRT < 100 kΩ 0.5 V FSW1 Switching frequency 1 VIN = 12 V, RRT = 100 kΩ to AGND 220 kHz FSW2 Switching frequency 2 VIN = 12 V, RRT = 9.52 kΩ to AGND 1.98 2.2 2.42 MHz FSW3 Switching frequency 3 VIN = 12 V, RRT = 220 kΩ to AGND 100 kHz SLOPE1 Internal slope compensation 1 RRT = 10 kΩ 500 mV/µs SLOPE2 Internal slope compensation 2 RRT = 100 kΩ 50 mV/µs tON(min) Minimum on-time 49 59 ns tOFF(min) Minimum off-time 60 85 ns
POWER GOOD (PG)
Falling with respect to the regulated V
AD
PG-UV Power Good UV trip level 90% 92% 94% voltage Rising with respect to the regulation VPG-OV Power Good OV trip level 108% 110% 112%
V
voltage
A
Falling with respect to the regulated VPG-UV-HYST Power Good UV hysteresis 3.4%
NCE INFO
output Rising with respect to the regulation VPG-OV-HYST Power Good OV hysteresis 3.4% voltage tPG-RISING-DLY OV filter time VOUT rising 25 µs tPG-FALL-DLY UV filter time VOUT falling 25 µs VPG-OL PG voltage Open collector, IPG = 4 mA 0.8 V
SYNCHRONIZATION OUTPUT (PG pin) R
CNFG pin = 54.9 kΩ or 71.5 kΩ to
MA
VSYNCOUT-LO SYNCOUT-LO low-state voltage 0.8 V VDDA (Primary), ISYNCOUT = 4 mA CNFG pin = 54.9 kΩ, or 71.5 kΩ to VSYNCOUT-HO SYNCOUT-HO high-state voltage 2.0 V
TION
VDDA (Primary) ISYNCOUT = 4 mA. Delay from HO rising edge to tSYNCOUT SYNCOUT (PGOOD pin in Primary VPFM = 0 V, FSW set by RRT = 100 kΩ 2.1 µs mode)
STARTUP (Soft Start)
tSS-INT Internal fixed soft-start time 1.9 2.8 3.6 ms
BOOT CIRCUIT
VBOOT-DROP Internal diode forward drop ICBOOT = 20 mA, VCC to CBOOT 0.63 0.8 V CBOOT to SW quiescent current, not IBOOT V switching EN = 5 V, VCBOOT-SW = 5 V 130 nA VBOOT-SW-UV-R CBOOT-SW UVLO rising threshold VCBOOT-SW falling 2.83 V VBOOT-SW-UV-F CBOOT-SW UVLO falling threshold VCBOOT-SW falling 2.59 V VBOOT-SW-UV-HYS CBOOT-SW UVLO hysteresis 0.24 V VHO-LOW HO low-state output voltage IHO = 100 mA 0.038 V
HIGH-SIDE GATE DRIVER (HO)
VHO-HIGH HO high-state output voltage IHO = –100 mA 0.08 V tHO-RISE HO rise time (10% to 90%) CLOAD = 2.7 nF 7 ns tHO-FALL HO fall time (90% to 10%) CLOAD = 2.7 nF 7 ns V I HO = VSW = 0 V, VCBOOT = 5 V, VVCCX HO-SRC HO peak source current 2.2 A = 5 V IHO-SINK HO peak sink current VVCCX = 5 V 3.2 A
LOW-SIDE GATE DRIVER (LO)
VLO-LOW LO low-state output voltage IHO = 100 mA 0.038 V VLO-HIGH LO high-state output voltage IHO = –100 mA 0.08 V tLO-RISE LO rise time (10% to 90%) CLOAD = 2.7 nF 7 ns 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM25149-Q1 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Description (continued) 6 Pin Configuration and Functions 6.1 Wettable Flanks 7 Specifications 7.1 Absolute Maximum Ratings 7.2 ESD Ratings  7.3 Recommended Operating Conditions 7.4 Thermal Information 7.5 Electrical Characteristics 7.6 Active EMI Filter 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Input Voltage Range (VIN) 8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA) 8.3.3 Enable (EN) 8.3.4 Power Good Monitor (PG) 8.3.5 Switching Frequency (RT) 8.3.6 Active EMI Filter 8.3.7 Dual Random Spread Spectrum (DRSS) 8.3.8 Soft-Start 8.3.9 Output Voltage Setpoint (FB) 8.3.10 Minimum Controllable On-Time 8.3.11 Error Amplifier and PWM Comparator (FB, EXTCOMP) 8.3.12 Slope Compensation 8.3.13 Inductor Current Sense (ISNS+, VOUT) 8.3.13.1 Shunt Current Sensing 8.3.13.2 Inductor DCR Current Sensing 8.3.14 Hiccup Mode Current Limiting 8.3.15 High-Side and Low-Side Gate Drivers (HO, LO) 8.3.16 Output Configurations (CNFG) 8.3.17 Single-Output Two-phase Operation 8.4 Device Functional Modes 8.4.1 Standby Modes 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC) 8.4.3 Thermal Shutdown 9 Application and Implementation 9.1 Application Information 9.1.1 Power Train Components 9.1.1.1 Buck Inductor 9.1.1.2 Output Capacitors 9.1.1.3 Input Capacitors 9.1.1.4 Power MOSFETs 9.1.1.5 EMI Filter 9.1.2 Error Amplifier and Compensation 9.2 Typical Application 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.2.1 Custom Design With WEBENCH® Tools 9.2.2.2 Custom Design With Excel Quickstart Tool 9.2.2.3 Buck Inductor 9.2.2.4 Current-Sense Resistance 9.2.2.5 Output Capacitors 9.2.2.6 Input Capacitors 9.2.2.7 Frequency Set Resistor 9.2.2.8 Feedback Resistors 9.2.2.9 Compensation Components 9.2.2.10 Active EMI Components 9.2.3 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.1.1 Power Stage Layout 11.1.2 Gate-Drive Layout 11.1.3 PWM Controller Layout 11.1.4 Active EMI Layout 11.1.5 Thermal Design and Layout 11.1.6 Ground Plane Design 11.2 Layout Example 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.2 Custom Design With WEBENCH® Tools 12.2 Documentation Support 12.2.1 Related Documentation 12.2.1.1 PCB Layout Resources 12.2.1.2 Thermal Design Resources 12.3 Receiving Notification of Documentation Updates 12.4 Support Resources 12.5 Trademarks 12.6 Electrostatic Discharge Caution 12.7 Glossary 13 Mechanical, Packaging, and Orderable Information