Datasheet MASTERGAN4 (STMicroelectronics) - 7
| Hersteller | STMicroelectronics |
| Beschreibung | High power density 600V half-bridge driver with two enhancement mode GaN HEMT |
| Seiten / Seite | 27 / 7 — MASTERGAN4. Driver. Symbol. Parameter. Test condition. Min Typ Max Unit. … |
| Dateiformat / Größe | PDF / 480 Kb |
| Dokumentensprache | Englisch |
MASTERGAN4. Driver. Symbol. Parameter. Test condition. Min Typ Max Unit. Logic inputs. Over temperature protection. DS13686. Rev 1
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MASTERGAN4 Driver Symbol - Parameter Test condition Min Typ Max Unit Logic inputs
TJ = 25 °C 1.1 1.31 1.45 Vil Low level logic threshold voltage V Full Temperature range(5) 0.8 - - LIN, HIN, SD/OD TJ = 25 °C 2 2.17 2.5 Vih High level logic threshold voltage V Full Temperature range(5) - - 2.7 Vihys Logic input threshold hysteresis 0.7 0.96 1.2 V IINh Logic ‘1’ input bias current LIN, HIN = 5 V 23 33 55 μA IINl Logic ‘0’ input bias current LIN, HIN = GND - - 1 μA LIN, HIN Input pull-down RPD_IN LIN, HIN = 5 V 90 150 220 kΩ resistor ISDh SD/OD Logic “1” input bias current SD/OD = 5 V 11 15 20 μA ISDl SD/OD Logic “0” input bias current SD/OD = 0 V - - 1 μA SD/OD = 5 V RPD_SD SD/OD Pull-down resistor 250 330 450 kΩ OpenDrain OFF V Thermal shutdown unlatch TSD SD/OD T threshold J = 25 °C(6) 0.5 0.75 1 V T R J = 25 °C; ON_OD SD/OD Open drain ON resistance 8 10 18 Ω IOD = 400 mV(6) T I J = 25 °C; OL_OD SD/OD Open Drain low level sink current 22 40 50 mA VOD = 400 mV(6) Td_GL LIN, GL Prop. delay from LIN to GL (6) - 46 - ns Td_GH HIN, GH Prop. delay from HIN to GH (6) - 46 - ns
Over temperature protection
TTSD - Shut down temperature (5) - 175 - °C THYS - Temperature hysteresis (5) - 20 - °C 1. VCC UVLO is referred to VCC - GND 2. Turn on and turn off total resistances include the values of the gate resistors and the driver Rdson 3. VBO = VBOOT - VOUT 4. RBD(on) is tested in the following way RBD(on) = [(VCC - VBOOTa) - (VCC - VBOOTb)] / [Ia - Ib] Where: Ia is BOOT pin current when VBOOT = VBOOTa; Ib is BOOT pin current when VBOOT = VBOOTb 5. Range estimated by characterization, not tested in production 6. Tested at wafer level
DS13686
-
Rev 1 page 7/27
Document Outline Features Applications Description 1 Block diagram 2 Pin descriptions and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history
MASTERGAN4 Driver Symbol - Parameter Test condition Min Typ Max Unit Logic inputs
TJ = 25 °C 1.1 1.31 1.45 Vil Low level logic threshold voltage V Full Temperature range(5) 0.8 - - LIN, HIN, SD/OD TJ = 25 °C 2 2.17 2.5 Vih High level logic threshold voltage V Full Temperature range(5) - - 2.7 Vihys Logic input threshold hysteresis 0.7 0.96 1.2 V IINh Logic ‘1’ input bias current LIN, HIN = 5 V 23 33 55 μA IINl Logic ‘0’ input bias current LIN, HIN = GND - - 1 μA LIN, HIN Input pull-down RPD_IN LIN, HIN = 5 V 90 150 220 kΩ resistor ISDh SD/OD Logic “1” input bias current SD/OD = 5 V 11 15 20 μA ISDl SD/OD Logic “0” input bias current SD/OD = 0 V - - 1 μA SD/OD = 5 V RPD_SD SD/OD Pull-down resistor 250 330 450 kΩ OpenDrain OFF V Thermal shutdown unlatch TSD SD/OD T threshold J = 25 °C(6) 0.5 0.75 1 V T R J = 25 °C; ON_OD SD/OD Open drain ON resistance 8 10 18 Ω IOD = 400 mV(6) T I J = 25 °C; OL_OD SD/OD Open Drain low level sink current 22 40 50 mA VOD = 400 mV(6) Td_GL LIN, GL Prop. delay from LIN to GL (6) - 46 - ns Td_GH HIN, GH Prop. delay from HIN to GH (6) - 46 - ns
Over temperature protection
TTSD - Shut down temperature (5) - 175 - °C THYS - Temperature hysteresis (5) - 20 - °C 1. VCC UVLO is referred to VCC - GND 2. Turn on and turn off total resistances include the values of the gate resistors and the driver Rdson 3. VBO = VBOOT - VOUT 4. RBD(on) is tested in the following way RBD(on) = [(VCC - VBOOTa) - (VCC - VBOOTb)] / [Ia - Ib] Where: Ia is BOOT pin current when VBOOT = VBOOTa; Ib is BOOT pin current when VBOOT = VBOOTb 5. Range estimated by characterization, not tested in production 6. Tested at wafer level
DS13686
-
Rev 1 page 7/27
Document Outline Features Applications Description 1 Block diagram 2 Pin descriptions and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history