Datasheet LM73100 (Texas Instruments) - 3

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LM7310 www.ti.com
SNOSDC0A – OCTOBER 2020 – REVISED DECEMBER 2020
5 Pin Configuration and Functions
VIN VOUT EN/UVLO 1 10 DNC OVLO 2 9 IMON 5 6 PG GND 3 8 PGTH DVDT 4 7
Figure 5-1. LM73100 RPW Package 10-Pin QFN Top View Table 5-1. Pin Functions PIN TYPE DESCRIPTION NAME NO.
Active High Enable for the device. A Resistor Divider on this pin from input supply to GND Analog EN/UVLO 1 can be used to adjust the Undervoltage Lockout threshold.
Do not leave floating.
Refer to Input Section 7.3.2 for more details. A Resistor Divider on this pin from supply to GND can be used to adjust the Overvoltage Analog OVLO 2 Lockout threshold. This pin can also be used as an Active Low Enable for the device.
Do
Input
not leave floating.
Refer to Section 7.3.3 for more details. Power Good indication. This is an Open Drain signal which is asserted High when the Digital PG 3 internal powerpath is fully turned ON and PGTH input exceeds a certain threshold. Refer Output to Section 7.3.9 for more details. Analog PGTH 4 Power Good Threshold. Refer to Section 7.3.9 for more details. Input IN 5 Power Power Input. OUT 6 Power Power Output. Analog A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating DVDT 7 Output for the fastest turn on slew rate. Refer to Section 7.3.4.1 for more details. GND 8 Ground This is the ground reference for all internal circuits and must be connected to system GND. Analog load current monitor. The pin voltage can be used to monitor the output load current. An external resistor from this pin to ground sets the current monitor gain. Analog IMON 9 Recommended to connect external clamp to limit the voltage below abs max rating in case Output of large current spikes. Connect to ground if not used.
Do not leave floating.
Refer to Section 7.3.5 for more details. DNC 10 X Internal test pin. Do not connect anything on this pin. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LM7310 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Timing Requirements 6.7 Switching Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Reverse Polarity Protection 7.3.2 Undervoltage Protection (UVLO & UVP) 7.3.3 Overvoltage Lockout (OVLO) 7.3.4 Inrush Current control and Fast-trip 7.3.4.1 Slew Rate (dVdt) and Inrush Current Control 7.3.4.2 Fast-Trip During Steady State 7.3.5 Analog Load Current Monitor Output 7.3.6 Reverse Current Protection 7.3.7 Overtemperature Protection (OTP) 7.3.8 Fault Response 7.3.9 Power Good Indication (PG) 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Single Device, Self-Controlled 8.2.1 Typical Application 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds 8.2.1.2.2 Setting Output Voltage Rise Time (tR) 8.2.1.2.3 Setting Power Good Assertion Threshold 8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range 8.2.1.3 Application Curves 8.3 Active ORing 8.4 Priority Power MUXing 8.5 USB PD Port Protection 8.6 Parallel Operation 9 Power Supply Recommendations 9.1 Transient Protection 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information