Datasheet A17700 (Allegro) - 6

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Pressure Sensor Interface and Signal Conditioning IC A17700 with Polynomial Signal Compensation and Advanced Diagnostics OPERATING CHARACTERISTICS:
Valid over the full supply voltage and ambient temperature ranges, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS
Supply Voltage VCC 4.5 5 5.5 V Supply Current ICC Excluding external bridge and output load – 6 10 mA Supply Zener Clamp Voltage VZsup ICC = ICC(max) + 30 mA; TA = 25°C 24 – – V Reverse Supply Zener Clamp Voltage VRZsup ICC = –25 mA; TA = 25°C – – –18 V Time between min VCC reached and analog Power-On Time [1] tPO output reaches 90% of final value; – – 1 ms bandwidth (BW) >1.2 kHz VPOR(R) VCC rising; see Figure 3 3.6 – 4.0 V Power-On Reset Voltage VPOR(F) VCC falling; see Figure 3 3.3 – 3.8 V VPOR(hys) Hysteresis 100 – 500 mV VUVD(R) VCC rising, TA = 25°C; see Figure 3 4.1 – 4.5 V Undervoltage Detection VUVD(F) VCC falling, TA = 25°C; see Figure 3 4.0 – 4.4 V VUVD(hys) Hysteresis 70 – 500 mV VOVD(R) VCC rising, TA = 25°C; see Figure 3 5.7 – 6 V Overvoltage Detection VOVD(F) VCC falling, TA = 25°C; see Figure 3 5.5 – 5.8 V VOVD(hys) Hysteresis 100 – 500 mV Initial Bandwidth [1] BW2.5 Default bandwidth setting – 2.5 – kHz Programmable Operating Bandwidth Range [1][2] BWprog Set by programming the digital low-pass filter 0.3 – 20 kHz Initial Output Response Time [2] tresp-Init Bandwidth option: BW2.5 – 250 – µs
BRIDGE ELECTRICAL CHARACTERISTICS
Bridge Supply Voltage VBRG Voltage supplied to transducer bridge 3.15 3.3 3.45 V Bridge Resistance RBRG Resistance of transducer bridge 1.5 – 10 kΩ Bridge Bypass Capacitor CBRG Bypass capacitor 80 100 150 nF
ANALOG FRONT END CHARACTERISTICS
Differential Input (V Gain1 = 3×, Gain2 = 1×, Offsetcoarse = 0, P-VN) VIN VBRG = 3.3 V –290 – 290 mV ADC Input Range [3] ADCIN –263 – 263 mV/V Bridge Sensitivity [1][3] BRGsens VP-VN at maximum input stimulus 10 – 80 mV/V Gain1 Trim bits – 2 – bits Bridge Sensitivity Programming Bits – Gain2 Trim bits – 4 – bits Bridge Offset [1][3] OFFSET Differential output offset, VP-VN, no input stimulus; coarse Scales with Gain1; Gain1 = 3×; see Table 4 –80 – 80 mV/V Bridge Offset Programming Bits – Number of Offset trim bits – 6 – bits Bridge Offset Programming Step Size OFFSETstp Scales with Gain1; Gain1 = 3×; see Table 4 – 2.667 – mV/V Polarity Bit pol_bit Inverts the polarity of bridge input, in digital domain – 1 – bit [1] Guaranteed by design. Not tested in production. [2] See Bandwidth selection in Functional Description section for details. [3] Analog front end gain and differential offset can be adjusted to adapt the bridge signal to the chip ADC input range. Note that offset scales with Gain 1 (Table 4). See Front End Gain and Offset Adjustment or Input Signal range calculation sections for details. 6 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Functional Block Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Pinout Diagram and Terminal List Operating Characteristics Functional Description Bandwidth Selection Output Response Time Power-On Time Front End Gain Adjustment Front End Differential Offset Adjustment Input Signal Range Calculation Fine Adjustment and Temperature Compensation Output Protocols Digital Output Mode Selection Digital Output Driver Fall Time Selection Broken Wire Detection Diagnostic Features Programming: Manchester Communication Entering Manchester Coding Manchester Interface Message Structure CRC Device Access Shadow Registers Device EEPROM and Register Access Lock EEPROM Map Volatile Registers Map Power Derating Package Outline Drawing