Datasheet ADSP-BF504 (Analog Devices) - 6

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ADSP-BF504 Booting
inputs to support the peripherals of the processor. Table 2 describes the inputs to the CEC, identifies their names in the The processor contains a small on-chip boot kernel, which con- event vector table (EVT), and lists their priorities. figures the appropriate peripheral for booting. If the processor is configured to boot from boot ROM memory space, the proces-
Table 2. Core Event Controller (CEC)
sor starts executing from the on-chip boot ROM. For more information, see Booting Modes.
Priority Event Handling (0 is Highest) Event Class EVT Entry
0 E mulation/Test Control EMU The event controller on the processor handles all asynchronous and synchronous events to the processor. The processor pro- 1 Reset RST vides event handling that supports both nesting and 2 Nonmaskable Interrupt NMI prioritization. Nesting allows multiple event service routines to 3 Exception EVX be active simultaneously. Prioritization ensures that servicing of 4 Reserved — a higher priority event takes precedence over servicing of a 5 Hardware Error IVHW lower priority event. The controller provides support for five different types of events: 6 Core Timer IVTMR 7 General-Purpose Interrupt 7 IVG7 • Emulation—An emulation event causes the processor to enter emulation mode, allowing command and control of 8 General-Purpose Interrupt 8 IVG8 the processor via the JTAG interface. 9 General-Purpose Interrupt 9 IVG9 • Reset—This event resets the processor. 10 General-Purpose Interrupt 10 IVG10 • Nonmaskable Interrupt (NMI)—The NMI event can be 11 General-Purpose Interrupt 11 IVG11 generated either by the software watchdog timer, by the 12 General-Purpose Interrupt 12 IVG12 NMI input signal to the processor, or by software. The 13 General-Purpose Interrupt 13 IVG13 NMI event is frequently used as a power-down indicator to 14 General-Purpose Interrupt 14 IVG14 initiate an orderly shutdown of the system. 15 General-Purpose Interrupt 15 IVG15 • Exceptions—Events that occur synchronously to program flow (in other words, the exception is taken before the
System Interrupt Controller (SIC)
instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause The system interrupt controller provides the mapping and exceptions. routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. • Interrupts—Events that occur asynchronously to program Although the processor provides a default mapping, the user flow. They are caused by input signals, timers, and other can alter the mappings and priorities of interrupt events by peripherals, as well as by an explicit software instruction. writing the appropriate values into the interrupt assignment Each event type has an associated register to hold the return registers (SIC_IARx). Table 3 describes the inputs into the SIC address and an associated return-from-event instruction. When and the default mappings into the CEC. an event is triggered, an interrupt service routine (ISR) must save the state of the processor to the supervisor stack. The processor event controller consists of two stages: the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. Conceptu- ally, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt Rev. C | Page 6 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide