Datasheet AD5749 (Analog Devices) - 4

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AD5749 Data Sheet Parameter1 Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS2 Current Loop Compliance 0 AVDD − 2.75 V Voltage Resistive Load Chosen such that compliance is not exceeded Inductive Load See the Test Conditions/ H Needs appropriate capacitor at higher inductance Comments column values; see the Driving Inductive Loads section Settling Time 4 mA to 20 mA, Full-Scale 8.5 μs 250 Ω load Step 120 μA Step, 4 mA to 1.2 μs 250 Ω load 20 mA Range DC PSRR 1 μA/V Output Impedance 130 MΩ DIGITAL INPUTS2 JEDEC compliant Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current −1 +1 μA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS2 FAULT, IFAULT, TEMP VOL, Output Low Voltage 0.4 V 10 kΩ pull-up resistor to DVCC 0.6 V At 2.5 mA VOH, Output High Voltage 3.6 V 10 kΩ pull-up resistor to DVCC SDO VOL, Output Low Voltage 0.5 0.5 V Sinking 200 μA VOH, Output High Voltage DVCC − 0.5 DVCC − 0.5 V Sourcing 200 μA High Impedance Output 3 pF Capacitance High Impedance Leakage −1 +1 μA Current POWER REQUIREMENTS AVDD 10.8 55 V DVCC Input Voltage 2.7 5.5 V AIDD 4.4 5.6 mA Output unloaded, output disabled; R3, R2, R1, R0 = 0000, RSET = 0 5.2 6.2 mA Output enabled DICC 0.3 1 mA VIH = DVCC, VIL = GND Power Dissipation 108 mW AVDD = 24 V, output unloaded 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization, not production tested. Rev. E | Page 4 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY TIMING CHARACTERISTICS Timing Diagrams ESD CAUTION SOFTWARE MODE CURRENT OUTPUT ARCHITECTURE DRIVING INDUCTIVE LOADS POWER-ON STATE OF THE AD5749 DEFAULT REGISTERS AT POWER-ON RESET FUNCTION OUTEN SOFTWARE CONTROL Input Shift Register Status Bit Read Operation HARDWARE CONTROL TRANSFER FUNCTION OUTPUT FAULT ALERT—SOFTWARE MODE OUTPUT FAULT ALERT—HARDWARE MODE ASYNCHRONOUS CLEAR (CLEAR) EXTERNAL CURRENT SETTING RESISTOR PROGRAMMABLE OVERRANGE MODES PACKET ERROR CHECKING TRANSIENT VOLTAGE PROTECTION THERMAL CONSIDERATIONS LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING ORDERING GUIDE