Datasheet AD5522 (Analog Devices) - 10

link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11
AD5522 Data Sheet Parameter Min Typ1 Max Unit Test Conditions/Comments
DIE TEMPERATURE SENSOR Accuracy2 ±7 °C Output Voltage at 25°C 1.5 V Output Scale Factor2 4.6 mV/°C Output Voltage Range2 0 3 V INTERACTION AND CROSSTALK2 DC Crosstalk (FOHx) 0.05 0.65 mV DC change resulting from a dc change in any DAC in the device, FV and FI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ DC Crosstalk (MEASOUTx) 0.05 0.65 mV DC change resulting from a dc change in any DAC in the device, MV and MI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ DC Crosstalk Within a Channel 0.05 mV All channels in FVMI mode, one channel at midscale, measure the current for one channel in the lowest current range for a change in comparator or clamp DAC levels for that PMU SPI INTERFACE LOGIC INPUTS Input High Voltage, VIH 1.7/2.0 V (2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant input levels Input Low Voltage, VIL 0.7/0.8 V (2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant input levels Input Current, IINH, IINL −1 +1 µA Input Capacitance, C 2 IN 10 pF CMOS LOGIC OUTPUTS SDO, CPOx Output High Voltage, VOH DVCC − 0.4 V Output Low Voltage, VOL 0.4 V IOL = 500 µA Tristate Leakage Current −2 +2 µA SDO, CPOH1/SDO −1 +1 µA Al other output pins Output Capacitance2 10 pF OPEN-DRAIN LOGIC OUTPUTS BUSY, TMPALM, CGALM Output Low Voltage, VOL 0.4 V IOL = 500 µA, CLOAD = 50 pF, RPULLUP = 1 kΩ Output Capacitance2 10 pF LVDS INTERFACE LOGIC INPUTS REDUCED RANGE LINK2 Input Voltage Range 875 1575 mV Input Differential Threshold −100 +100 mV External Termination Resistance 80 100 120 Ω Differential Input Voltage 100 mV LVDS INTERFACE LOGIC OUTPUTS REDUCED RANGE LINK Output Offset Voltage 1200 mV Output Differential Voltage 400 mV POWER SUPPLIES AVDD 10 28 V |AVDD − AVSS| ≤ 33 V AVSS −23 −5 V DVCC 2.3 5.25 V AIDD 26 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled AISS −26 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled AIDD 28 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled AISS −28 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled AIDD 36 mA External range, excluding load conditions AISS −36 mA External range, excluding load conditions DICC 1.5 mA Maximum Power Dissipation2 7 W Maximum power that should be dissipated in this package under worst-case load conditions; careful consideration should be given to supply selection and thermal design Rev. F | Page 10 of 64 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Characteristics Circuit and Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Force Amplifier Comparators Clamps Current Range Selection High Current Ranges Measure Current Gains VMID Voltage Choosing Power Supply Rails Measure Output (MEASOUTx Pins) Device Under Test Ground (DUTGND) Guard Amplifier Compensation Capacitors System Force and Sense Switches Temperature Sensor DAC Levels Offset DAC Gain and Offset Registers Cached X2 Registers Gain and Offset Registers for the FIN DAC Gain and Offset Registers for the Comparator DACs Gain and Offset Registers for the Clamp DACs Reference Voltage (VREF) Reference Selection Reference Selection Example Calibration Reducing Zero-Scale Error Reducing Gain Error Calibration Example Additional Calibration System Level Calibration Circuit Operation Force Voltage (FV) Mode Force Current (FI) Mode Serial Interface SPI Interface LVDS Interface Serial Interface Write Mode RESETB Function BUSYB and LOADB Functions Register Update Rates Register Selection Readback Control, RD/WRB PMU Address Bits: PMU3, PMU2, PMU1, PMU0 NOP (No Operation) Reserved Commands Write System Control Register Write PMU Register Write DAC Register DAC Addressing Read Registers Readback of System Control Register Readback of PMU Register Readback of Comparator Status Register Readback of Alarm Status Register Readback of DAC Register Applications Information Power-On Default Setting Up the Device on Power-On Changing Modes Required External Components Power Supply Decoupling Power Supply Sequencing Typical Application for the AD5522 Outline Dimensions Ordering Guide