Datasheet ADA4320-1 (Analog Devices) - 7

ADA4320-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
P + – + – T T T T M U U U U CO VO VO VO VO 4 3 22 21 20 GND 1 19 GND GND 2 18 GND VCC 3 ADA4320-1 17 GND VCC 4 TOP VIEW 16 SLEEP VCC 5 (Not to Scale 15 CLK RAMP 6 14 SDATA TXEN 7 13 DATEN 82 92 10 11 12 D D – + N D N GN GN VI VI GN NOTES
5
1. EXPOSED THERMAL PAD MUST BE ELECTRICALLY AND
00
THERMALLY CONNECTED TO PCB GROUND (GND) PLANE.
707- 08 Figure 4. Pin Configuration, Top View
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 2, 8, 9, 12, GND Common External Ground Reference. 17, 18, 19, EPAD 3, 4, 5 VCC Common Positive External Supply Voltage. 6 RAMP External RAMP Capacitor (Optional). 7 TXEN Transmit Enable. Logic 0 disables forward transmission, and Logic 1 enables forward transmission. 10 VIN− Inverting Input. DC-biased to approximately VCC/2. This pin should be ac-coupled with a 0.1 μF capacitor. 11 VIN+ Noninverting Input. DC-biased to approximately VCC/2. This pin should be ac-coupled with a 0.1 μF capacitor. 13 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous, and simultaneously enables the register for serial data load). 14 SDATA Serial Data Input. This digital input allows an 8-bit serial control word to be loaded into the internal register with the most significant bit (MSB) first to adjust both the gain and current levels. 15 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave shift register. A Logic 0-to-1 transition latches the data bit, and a Logic 1-to-0 transition transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition. 16 SLEEP Low Power Sleep Mode. In sleep mode, the supply current is reduced to 12 μA typical. Logic 0 powers down the device, and Logic 1 powers up the device. 20, 22 VOUT− Negative Output Signal. This pin must be biased to VCC. 21, 23 VOUT+ Positive Output Signal. This pin must be biased to VCC. 24 COMP Internal Compensation. This pin must be externally decoupled (0.1 μF capacitor). Rev. A | Page 7 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE