Datasheet ADA4320-1 (Analog Devices) - 9

ADA4320-1
–10 80 ) TXEN = 1, ALL CURRENT LEVELS ) CURRENT LEVEL 3 TXEN = 0 BmV CURRENT LEVEL 0 –20 d BmV 70 H ( (d IDT –30 INT O 60 N P –40 IO BANDW S S 50 RE 60kHz –50 P M IN 1 R 40 E –60 B CO d W 1 O P UT E P 30 –70 IS UT O NO –80 20
3
0 6 12 18 24 30 36 42 48 54 60
14 -01
0 6 12 18 24 30 36 42 48 54 60
-0 07 07
GAIN CODE GAIN CODE
087 087 Figure 11. Noise Power vs. Gain Code Figure 14. Output 1 dB Compression Point vs. Gain Code
0 –40 80 SLEEP SINGLE QPSK CHANNEL TX DISABLE c) INPUT LEVEL = 29dBmV TX ENABLE B –45 CURRENT LEVEL 3 70 d –5 ( CHANNEL WIDTH = 6.4MHz IO DRIVEN CHANNEL CENTER = 42MHz B) d –50 ADJACENT CHANNEL WIDTH = 6.4MHz 60 ) ( ADJACENT CHANNEL CENTER = 48.4MHz V S –10 m S R RAT B O E –55 50 W (d O L E P URN L –15 –60 ACPR 40 V L T LE T RE T –65 30 U U –20 TP P CHANNE UT OU NT –70 OUTPUT 20 O LEVEL –25 CE JA –75 10 AD –30 –80 0
7
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
12
0 6 12 18 24 30 36 42 48 54 60
-0 01 7- 07
FREQUENCY (MHz) GAIN CODE
70 087 08 Figure 12. Output Return Loss (S22) vs. Frequency Figure 15. ACPR and Output Level vs. Gain Code
–61 –52 SINGLE QPSK CHANNEL CURRENT LEVEL 0 4× QAM64 CHANNELS (UNCORRELATED) c) OUTPUT LEVEL = 61dBmV CURRENT LEVEL 1 c) OUTPUT LEVEL = 53dBmV/CHANNEL B CURRENT LEVEL 2 B d –62 GAIN CODE 60 (MAXIMUM) d –54 GAIN CODE 60 (MAXIMUM) ( CURRENT LEVEL 3 CHANNEL WIDTH = 6.4MHz ( CHANNEL WIDTH = 1.6MHz IO ADJACENT CHANNEL WIDTH = 6.4MHz IO ADJACENT CHANNEL WIDTH = 1.6MHz –63 –56 R RAT R RAT E E CURRENT LEVEL 0 W CURRENT LEVEL 1 –64 W O –58 O CURRENT LEVEL 2 P P CURRENT LEVEL 3 L L –65 –60 CHANNE –66 CHANNE –62 NT NT CE CE JA –67 JA –64 AD AD –68 –66 5 15 25 35 45 55 65 75 85
15 16 0
5 15 25 35 45 55 65 75 85
0 7- 7-
FREQUENCY (MHz)
70
FREQUENCY (MHz)
70 08 08 Figure 13. ACPR vs. Frequency for Single QPSK Channel Figure 16. ACPR vs. Frequency for 4× QAM64 Channels Rev. A | Page 9 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE