Datasheet ADRF5549 (Analog Devices) - 4

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ADRF5549 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL INPUTS SWCTRL-ChAB and PD-ChAB Low (VIL) 0 0.7 V High (VIH)2 1.4 VDD V BP-ChA and BP-ChB Low (VIL) 0 0.3 V High (VIH)2 1.0 VDD V SUPPLY CURRENT (IDD) VDD1-Chx and VDD2-Chx = 5 V per channel High Gain Mode 85 mA Low Gain Mode 35 mA Power-Down Mode 12 mA Transmit Current (Switch) SWVDD-ChAB = 5 V 4.3 mA DIGITAL INPUT CURRENTS SWCTRL-ChAB, PD-ChAB, BP-ChA, and BP-ChB = 5 V per channel SWCTRL-ChAB 0.0004 mA PD-ChAB 0.2 mA BP-ChA and BP-ChB 0.4 mA 1 See Table 5 and Table 6. 2 VDD (shown in the maximum column) is the voltage of the SWVDD-CHAB, VDD1-CHA, VDD1-CHB, VDD2-CHA, and VDD2-CHB pins. 3 TCASE is measured at the exposed pad. Rev. A | Page 4 of 15 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION High Gain Mode Low Gain Mode TRANSMIT OPERATION THEORY OF OPERATION SIGNAL PATH SELECT Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE