Datasheet ADRF5549 (Analog Devices)

Dual-Channel, 1.8 GHz to 2.8 GHz, Receiver Front End Data Sheet ADRF5549 FEATURES FUNCTIONAL BLOCK DIAGRAM Integrated dual-channel RF front end ADRF5549 2-stage LNA and high power SPDT switch A A h A On-chip bias and matching Ch Ch M-C Single-supply operation C C ND ER ND ND ND DD1- C DD2- G T NI G G G V NI NI V Gain 40 39 38 37 36 35 34 33 32 31 High gain mode: 35 dB typical at 2.3 GHz Low gain mode: 17 dB typical at 2.3 GHz GND 1 30 GND GND 2 29 RxOUT-ChA Low noise figure ANT-ChA 3 28 GND GND 4 27 BP-ChA High gain mode: 1.4 dB typical at 2.3 GHz SWCTRL-ChAB 5 26 PD-ChAB SWVDD-ChAB 6 25 NIC Low gain mode: 1.4 dB typical at 2.3 GHz GND 7 24 BP-ChB ANT-ChB 8 23 GND High isolation GND 9 22 RxOUT-ChB GND 10 21 GND Between RxOUT-ChA and RxOUT-ChB: 50 dB typical Between TERM-ChA and TERM-ChB: 62 dB typical 11 12 13 14 15 16 17 18 19 20 Low insertion loss: 0.6 dB typical at 2.3 GHz B C B C C B ND h NI ND ND ND NI NI G G G G Ch Ch High power handling at TCASE = 105°C M-C
001
Full lifetime ER DD1- DD2- T V V
20828-
LTE average power (9 dB PAR): 40 dBm
Figure 1.
Single event (<10 sec operation) LTE average power (9 dB PAR): 43 dBm High OIP3: 32 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 85 mA typical at 5V Low gain mode: 35 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 6 mm × 6 mm, 40-lead LFCSP APPLICATIONS Wireless Infrastructure TDD massive multiple input and multiple output (MIMO) and active antenna systems TDD-based communication systems
In low gain mode, one stage of the two-stage LNA is in bypass
GENERAL DESCRIPTION
mode providing 17 dB of gain at a lower current of 35 mA. The ADRF5549 is a dual-channel, integrated, RF front-end In power-down mode, the LNAs are turned off, and the device multichip module designed for time division duplexing (TDD) draws 12 mA. applications that operates from 1.8 GHz to 2.8 GHz. The In transmit operation, when RF inputs are connected to a ADRF5549 is configured in dual channels with a cascading, termination pin (TERM-ChA or TERM-ChB), the switch two-stage, low noise amplifier (LNA) and a high power, silicon provides a low insertion loss of 0.6 dB and handles a long-term single-pole, double-throw (SPDT) switch. evolution (LTE) ful lifetime average (9 dB peak to average ratio In high gain mode, the cascaded two-stage LNA and switch (PAR)) of 40 dBm and 43 dBm for a 9 dB PAR LTE single event offer a low noise figure of 1.4 dB and a high gain of 35 dB with (<10 sec) average. The device comes in a RoHS-compliant, an output third-order intercept point (OIP3) of 32 dBm typical. compact, 6 mm × 6 mm, 40-lead, lead frame chip-scale package (LFCSP).
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION High Gain Mode Low Gain Mode TRANSMIT OPERATION THEORY OF OPERATION SIGNAL PATH SELECT Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE