Datasheet HMC637ALP5E (Analog Devices) - 9

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Data Sheet HMC637ALP5E APPLICATIONS INFORMATION
For the application circuit shown in Figure 21, VDD must be The power-down sequence is as follows: applied through a broadband bias tee or external bias network. 1. Remove VGG2 bias The power-up bias sequence is as follows: 2. Remove VDD bias 1. Set V 3. Remove VGG1 bias GG1 to −2 V 2. Set VDD to 12 V 3. Set VGG2 to 5 V 4. Adjust VGG1 to achieve IDD for 400 mA
C4 C7 1000pF 4.7µF + ACG1 ACG2 VDD 30 VGG2 2 C3 C1 29 1000pF 1000pF HMC637ALP5E 21 RFOUT 16 RFIN 5 ACG3 15 C8 + 4.7µF ACG4 13 C6 1000pF VGG1 C9 C2 C5
1 -02
4.7µF + 100pF 1000pF
308 17 Figure 21. Application Circuit Rev. C | Page 9 of 11 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Applications Information Evaluation PCB List of Materials for PCB EV1HMC637ALP5E Outline Dimensions Ordering Guide