Datasheet ADPA7002CHIP (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | GaAs, pHEMT, MMIC,1/2 W, 20 GHz to 44 GHz, Power Amplifier |
| Seiten / Seite | 23 / 5 — Data Sheet. ADPA7002CHIP. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Revision | C |
| Dateiformat / Größe | PDF / 532 Kb |
| Dokumentensprache | Englisch |
Data Sheet. ADPA7002CHIP. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GG1. DD1. DD2. DD3. DNB. GND. RFIN. RFOUT. TOP VIEW. (CIRCUIT SIDE). 21 20
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Data Sheet ADPA7002CHIP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A A A F GG1 DD1 DD2 DD3 RE DNB V DNB V V DNB V DNB V 2 4 3 5 6 7 8 9 10 11 GND ADPA7002CHIP RFIN 1 12 RFOUT TOP VIEW (CIRCUIT SIDE) GND 22 21 20 19 18 17 16 15 14 13 B B B B T DNB DNB DE GG1 DD1 DD2 DNB DD3 DNB V V V V V NOTES
002
1. DNB = DO NOT BOND. THESE PADS ARE NOT BONDED.
17236- Figure 2. Pad Configuration
Table 5. Pad Function Descriptions Pad No. Mnemonic Description
1 RFIN RF Signal Input. This pad is ac-coupled and matched to 50 Ω. 2, 4, 7, 9, 14, 16, 19, 21 DNB Do Not Bond. These pads are not bonded. 3 VGG1A Gate Control for the Amplifier. VGG1A is used with the alternate assembly configuration. External bypass capacitors of 4.7 µF and 0.01 µF are required (see Figure 57). 5, 6, 8 VDD1A, VDD2A, VDD3A Drain Biases for the Amplifier. VDD1A, VDD2A, VDD3A, are used with the alternate assembly configuration. External bypass capacitors of 4.7 µF and 0.01 µF are required (see Figure 57). 10 VREF Reference Diode for Temperature Compensation of VDET RF Output Power Measurements. 11, 22, Die Bottom GND Grounds. These pads and the die bottom must be connected to RF and dc ground. 12 RFOUT RF Signal Output. This pad is ac-coupled and matched to 50 Ω. 13 VDET Detector Diode to Measure RF Output Power. Output power detection via this pad requires the application of a dc bias voltage through an external series resistor. Used in combination with the VREF pad, the difference voltage (VREF − VDET) is a temperature compensated dc voltage that is proportional to the RF output power. 15, 17, 18 VDD1B, VDD2B, VDD3B Drain Biases for the Amplifier. External bypass capacitors of 4.7 µF and 0.01 µF are required (see Figure 53). 20 VGG1B Gate Control for the Amplifier. External bypass capacitors of 4.7 µF and 0.01 µF are required (see Figure 53). Rev. C | Page 5 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS CONSTANT DRAIN CURRENT (IDD) OPERATION THEORY OF OPERATION ADPA7002CHIP ASSEMBLY AND CIRCUIT DIAGRAMS ALTERNATE ASSEMBLY DIAGRAM BIASING PROCEDURES BIASING THE ADPA7002CHIP WITH THE HMC980LP4E Application Circuit Setup Limiting VGATE to Meet ADPA7002CHIP VGGx AMR Requirement HMC980LP4E Bias Sequence Constant Drain Current Bias vs. Constant Gate Voltage Bias MOUNTING AND BONDING TECHNIQUES FOR MILLIMETER WAVE GAAS MMICS Handling Precautions Mounting Wire Bonding OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADPA7002CHIP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A A A F GG1 DD1 DD2 DD3 RE DNB V DNB V V DNB V DNB V 2 4 3 5 6 7 8 9 10 11 GND ADPA7002CHIP RFIN 1 12 RFOUT TOP VIEW (CIRCUIT SIDE) GND 22 21 20 19 18 17 16 15 14 13 B B B B T DNB DNB DE GG1 DD1 DD2 DNB DD3 DNB V V V V V NOTES
002
1. DNB = DO NOT BOND. THESE PADS ARE NOT BONDED.
17236- Figure 2. Pad Configuration
Table 5. Pad Function Descriptions Pad No. Mnemonic Description
1 RFIN RF Signal Input. This pad is ac-coupled and matched to 50 Ω. 2, 4, 7, 9, 14, 16, 19, 21 DNB Do Not Bond. These pads are not bonded. 3 VGG1A Gate Control for the Amplifier. VGG1A is used with the alternate assembly configuration. External bypass capacitors of 4.7 µF and 0.01 µF are required (see Figure 57). 5, 6, 8 VDD1A, VDD2A, VDD3A Drain Biases for the Amplifier. VDD1A, VDD2A, VDD3A, are used with the alternate assembly configuration. External bypass capacitors of 4.7 µF and 0.01 µF are required (see Figure 57). 10 VREF Reference Diode for Temperature Compensation of VDET RF Output Power Measurements. 11, 22, Die Bottom GND Grounds. These pads and the die bottom must be connected to RF and dc ground. 12 RFOUT RF Signal Output. This pad is ac-coupled and matched to 50 Ω. 13 VDET Detector Diode to Measure RF Output Power. Output power detection via this pad requires the application of a dc bias voltage through an external series resistor. Used in combination with the VREF pad, the difference voltage (VREF − VDET) is a temperature compensated dc voltage that is proportional to the RF output power. 15, 17, 18 VDD1B, VDD2B, VDD3B Drain Biases for the Amplifier. External bypass capacitors of 4.7 µF and 0.01 µF are required (see Figure 53). 20 VGG1B Gate Control for the Amplifier. External bypass capacitors of 4.7 µF and 0.01 µF are required (see Figure 53). Rev. C | Page 5 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS CONSTANT DRAIN CURRENT (IDD) OPERATION THEORY OF OPERATION ADPA7002CHIP ASSEMBLY AND CIRCUIT DIAGRAMS ALTERNATE ASSEMBLY DIAGRAM BIASING PROCEDURES BIASING THE ADPA7002CHIP WITH THE HMC980LP4E Application Circuit Setup Limiting VGATE to Meet ADPA7002CHIP VGGx AMR Requirement HMC980LP4E Bias Sequence Constant Drain Current Bias vs. Constant Gate Voltage Bias MOUNTING AND BONDING TECHNIQUES FOR MILLIMETER WAVE GAAS MMICS Handling Precautions Mounting Wire Bonding OUTLINE DIMENSIONS ORDERING GUIDE