Datasheet ADPA7002CHIP (Analog Devices) - 4

ADPA7002CHIP Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Rating
Thermal performance is directly linked to system design and V operating environment. Careful attention to printed circuit DDx 6.0 V V board (PCB) thermal design is required. GG1 −1.6 V to 0 V RF Input Power (RFIN) 25 dBm θJC is the channel to case thermal resistance, channel to bottom Continuous Power Dissipation (PDISS), 6.77 W of die. TA = 85°C (Derate 75.2 mW/°C above 85°C)
Table 4. Thermal Resistance
Temperature
Package Type θJC Unit
Storage Range −65°C to +150°C C-22-31 13.3 °C/W Operating Range −55°C to +85°C 1 θ Nominal Junction (T JC was determined by simulation under the following conditions: the heat A = 85°C, VDD = 5 V, 124.9°C transfer is due solely to thermal conduction from the channel through the IDQ = 600 mA) ground pad to the PCB, and the ground pad is held constant at the Junction to Maintain 1,000,000 Hour 175°C operating temperature of 85°C. Mean Time to Failure (MTTF) Electrostatic Discharge (ESD) Sensitivity
ESD CAUTION
Human Body Model (HBM) Class 1A (passed 500 V) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 4 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS CONSTANT DRAIN CURRENT (IDD) OPERATION THEORY OF OPERATION ADPA7002CHIP ASSEMBLY AND CIRCUIT DIAGRAMS ALTERNATE ASSEMBLY DIAGRAM BIASING PROCEDURES BIASING THE ADPA7002CHIP WITH THE HMC980LP4E Application Circuit Setup Limiting VGATE to Meet ADPA7002CHIP VGGx AMR Requirement HMC980LP4E Bias Sequence Constant Drain Current Bias vs. Constant Gate Voltage Bias MOUNTING AND BONDING TECHNIQUES FOR MILLIMETER WAVE GAAS MMICS Handling Precautions Mounting Wire Bonding OUTLINE DIMENSIONS ORDERING GUIDE