Datasheet LT8610AC, LT8610AC-1 (Analog Devices) - 9

HerstellerAnalog Devices
Beschreibung42V, 3.5A Synchronous Step-Down Regulator with 2.5µA Quiescent Current
Seiten / Seite26 / 9 — PIN FUNCTIONS SYNC (Pin 1):. SW (Pins 9, 10, 11):. BST (Pin 12):. TR/SS …
RevisionB
Dateiformat / GrößePDF / 2.0 Mb
DokumentenspracheEnglisch

PIN FUNCTIONS SYNC (Pin 1):. SW (Pins 9, 10, 11):. BST (Pin 12):. TR/SS (Pin 2):. INTV. CC (Pin 13):. BIAS (Pin 14):. RT (Pin 3):

PIN FUNCTIONS SYNC (Pin 1): SW (Pins 9, 10, 11): BST (Pin 12): TR/SS (Pin 2): INTV CC (Pin 13): BIAS (Pin 14): RT (Pin 3):

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LT8610AC/LT8610AC-1
PIN FUNCTIONS SYNC (Pin 1):
External Clock Synchronization Input.
SW (Pins 9, 10, 11):
The SW pins are the outputs of the Ground this pin for low ripple Burst Mode operation at low internal power switches. Tie these pins together and con- output loads. Tie to a clock source for synchronization to nect them to the inductor and boost capacitor. This node an external frequency. Apply a DC voltage of 3V or higher should be kept small on the PCB for good performance. or tie to INTVCC for pulse-skipping mode. When in pulse-
BST (Pin 12):
This pin is used to provide a drive voltage, skipping mode, the IQ will increase to several hundred µA. higher than the input voltage, to the topside power switch. Do not float this pin. Place a 0.1µF boost capacitor as close as possible to the IC.
TR/SS (Pin 2):
Output Tracking and Soft-Start Pin. This
INTV
pin allows user control of output voltage ramp rate during
CC (Pin 13):
Internal 3.4V Regulator Bypass Pin. The internal power drivers and control circuits are pow- start-up. A TR/SS voltage below 0.8V forces the LT8610AC/ ered from this voltage. INTV LT8610AC-1 to regulate the FB pin to equal the TR/SS pin CC maximum output cur- rent is 20mA. Do not load the INTV voltage. When TR/SS is above 0.8V, the tracking function CC pin with external circuitry. INTV is disabled and the internal reference resumes control of CC current will be supplied from BIAS if V the error amplifier. An internal 2.2μA pull-up current from BIAS > 3.1V, otherwise current will be drawn from VIN. Voltage on INTV INTV CC will vary between 2.8V and 3.4V when CC on this pin allows a capacitor to program output V voltage slew rate. This pin is pulled to ground with an BIAS is between 3.0V and 3.6V. Decouple this pin to power ground with at least a 1μF low ESR ceramic capacitor internal 230Ω MOSFET during shutdown and fault condi- placed close to the IC. tions; use a series resistor if driving from a low impedance output. This pin may be left floating in the LT8610AC if
BIAS (Pin 14):
The internal regulator will draw current from the tracking function is not needed. A minimum of 100pF BIAS instead of VIN when BIAS is tied to a voltage higher of external capacitance must be used on the LT8610AC-1. than 3.1V. For output voltages of 3.3V and above this pin should be tied to V
RT (Pin 3):
A resistor is tied between RT and ground to OUT. If this pin is tied to a supply other than V set the switching frequency. OUT use a 1µF local bypass capacitor on this pin.
PG (Pin 15):
The PG pin is the open-drain output of an
EN/UV (Pin 4):
The LT8610AC/LT8610AC-1 is shut down internal comparator. PG remains low until the FB pin is when this pin is low and active when this pin is high. within ±8% of the final regulation voltage, and there are The hysteretic threshold voltage is 1.015V going up and no fault conditions. PG is valid when V 0.97V going down. Tie to V IN is above 3.0V, IN if the shutdown feature is regardless of EN/UV pin state. not used. An external resistor divider from VIN can be used to program a VIN threshold below which the LT8610AC/
FB (Pin 16):
The LT8610AC/LT8610AC-1 regulates the FB LT8610AC-1 will shut down. pin to 0.800V. Connect the feedback resistor divider tap to this pin. Also, connect a phase lead capacitor between
VIN (Pins 5, 6):
The VIN pins supply current to the FB and V LT8610AC/LT8610AC-1 internal circuitry and to the internal OUT. Typically, this capacitor is 4.7pF to 10pF. topside power switch. These pins must be tied together
GND (Pin 8, Exposed Pad Pin 17):
Ground. These pins and be locally bypassed. Be sure to place the positive are the return path of the internal bottom-side switch and terminal of the input capacitor as close as possible to the must be tied together. Place the negative terminal of the VIN pins, and the negative capacitor terminal as close as input capacitor as close to the GND pin and exposed pad possible to the GND pins. as possible. The exposed pad must be soldered to the PCB in order to lower the thermal resistance.
NC (Pin 7):
No Connect. This pin is not connected to internal circuitry. Rev. B For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts