Datasheet PUSB3BB2DF (Nexperia) - 10
| Hersteller | Nexperia |
| Beschreibung | Extremely low clamping low capacitance ESD protection |
| Seiten / Seite | 15 / 10 — Nexperia. PUSB3BB2DF. Extremely low clamping low capacitance ESD … |
| Revision | 03112020 |
| Dateiformat / Größe | PDF / 1.9 Mb |
| Dokumentensprache | Englisch |
Nexperia. PUSB3BB2DF. Extremely low clamping low capacitance ESD protection
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Nexperia PUSB3BB2DF Extremely low clamping low capacitance ESD protection
aaa-030889 8 aaa-030890 0 IPP IPP (A) (A) 6 -2 4 -4 2 -6 0 -8 0 2 4 6 8 -8 -6 -4 -2 0 VCL (V) VCL (V) IEC 61000-4-5; tp = 8/20 µs; positive pulse IEC 61000-4-5; tp = 8/20 µs; negative pulse
Fig. 18. Dynamic resistance with positive clamping; Fig. 19. Dynamic resistance with negative clamping; typical values typical values 10. Application information
The device is designed for the protection of two signal lines from surge pulses and ESD damage. The device is suitable on lines where the signal polarities are both, positive and negative with respect to ground. The device uses an advanced clamping structure showing a negative dynamic resistance. This snap-back behavior strongly reduces the clamping voltage system behind the ESD protection during an ESD event. Do not connect unlimited DC current sources to the data lines to avoid keeping the ESD protection device snap-back state after exceeding breakdown voltage (due to an ESD pulse for instance). lines to be protected ESD protection diode GND aaa-030287
Fig. 20. Application diagram Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended:
1.
Place the device as close to the input terminal or connector as possible.
2.
Minimize the path length between the device and the protected line.
3.
Keep parallel signal paths to a minimum.
4.
Avoid running protected conductors in paral el with unprotected conductors.
5.
Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops.
6.
Minimize the length of the transient return path to ground.
7.
Avoid using shared transient return paths to a common ground point.
8.
Use ground planes whenever possible. For multilayer PCBs, use ground vias. PUSB3BB2DF All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. Al rights reserved
Product data sheet 3 November 2020 10 / 15
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Quick reference data 5. Pinning information 6. Ordering information 7. Marking 8. Limiting values 9. Characteristics 10. Application information 11. Package outline 12. Soldering 13. Revision history 14. Legal information Contents
aaa-030889 8 aaa-030890 0 IPP IPP (A) (A) 6 -2 4 -4 2 -6 0 -8 0 2 4 6 8 -8 -6 -4 -2 0 VCL (V) VCL (V) IEC 61000-4-5; tp = 8/20 µs; positive pulse IEC 61000-4-5; tp = 8/20 µs; negative pulse
Fig. 18. Dynamic resistance with positive clamping; Fig. 19. Dynamic resistance with negative clamping; typical values typical values 10. Application information
The device is designed for the protection of two signal lines from surge pulses and ESD damage. The device is suitable on lines where the signal polarities are both, positive and negative with respect to ground. The device uses an advanced clamping structure showing a negative dynamic resistance. This snap-back behavior strongly reduces the clamping voltage system behind the ESD protection during an ESD event. Do not connect unlimited DC current sources to the data lines to avoid keeping the ESD protection device snap-back state after exceeding breakdown voltage (due to an ESD pulse for instance). lines to be protected ESD protection diode GND aaa-030287
Fig. 20. Application diagram Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended:
1.
Place the device as close to the input terminal or connector as possible.
2.
Minimize the path length between the device and the protected line.
3.
Keep parallel signal paths to a minimum.
4.
Avoid running protected conductors in paral el with unprotected conductors.
5.
Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops.
6.
Minimize the length of the transient return path to ground.
7.
Avoid using shared transient return paths to a common ground point.
8.
Use ground planes whenever possible. For multilayer PCBs, use ground vias. PUSB3BB2DF All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. Al rights reserved
Product data sheet 3 November 2020 10 / 15
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Quick reference data 5. Pinning information 6. Ordering information 7. Marking 8. Limiting values 9. Characteristics 10. Application information 11. Package outline 12. Soldering 13. Revision history 14. Legal information Contents