Datasheet STM32WB5MMG (STMicroelectronics) - 5

STM32WB5MMG Pin description 4 Pin description
The following figure shows the module pinout package bottom view.
Figure 2. STM32WB5MMG module pinout: bottom view VSS ANT _NC 86 85 47 60 1 PB10 PB2 PC4 PA8 PA9 PA7 PA6 PA5 PA4 PA3 VSS ANT_IN RF_OUT VSS PA2 PB11 PA1 61 74 75 76 PC5 PA0 PD9 PD8 PD15 PH0 NC VREF+ 73 84 77 62 NC VSS PD4 VSS PD10 PH1 PE4 VDDA 72 PB12 83 78 63 PC3 PE3 PC8 PE2 PD14 PC13 PC2 PB6 PC1 71 82 79 64 PB15 NRST PC7 PD11 PE0 PE1 PB14 PB9 70 81 80 65 PC6 PC0 PD3 PD6 PD5 PD13 PH3- PB13 BOOT0 69 68 67 66 PD1 PB8 PC9 PD2 PD7 PD12 PD0 VBAT VDD VSS USB SMPS 31 17 VDD VSS PA11 PA12 PA10 PA15 PA14 PA13 PC12 PC11 PC10 PB3 PB4 PB5 PB7 SMPS DS13252
-
Rev 1 page 5/31
Document Outline 1 Introduction 2 Description 3 Available peripherals 4 Pin description 5 Recommendations 5.1 Pin recommendations 5.2 Layout recommendations 5.2.1 STM32WB5MMG placement 5.2.2 Enclosure effects 5.2.3 Ground plane 5.2.4 Sensitive GPIOs 5.2.5 Four layer reference board design 6 Electrical characteristics 6.1 Operating conditions 6.2 Power consumption 6.3 RF characteristics 6.4 Antenna radiation patterns and efficiency 7 Thermal characteristics 8 Solder re-flow recommendation 9 Package information 9.1 SiP-LGA86 package information 9.1.1 Device marking for SiP-LGA86 10 Ordering information 11 Tape and reel packing 12 Certification 12.1 CE certification 12.2 FCC certification 12.3 ISED certification 12.4 JRF certification 12.5 NCC certification 12.6 SRRC certification Revision history Contents List of tables List of figures