Datasheet STDRIVE101 (STMicroelectronics) - 7
| Hersteller | STMicroelectronics |
| Beschreibung | Triple half-bridge gate driver |
| Seiten / Seite | 32 / 7 — STDRIVE101. Electrical characteristics. Symbol. Parameter. Test … |
| Dateiformat / Größe | PDF / 899 Kb |
| Dokumentensprache | Englisch |
STDRIVE101. Electrical characteristics. Symbol. Parameter. Test Condition. Min. Typ. Max. Unit. DS13472. Rev 1. page 7/32
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STDRIVE101 Electrical characteristics Symbol Parameter Test Condition Min. Typ. Max. Unit
VS = VREG12 = 5.5 V I Maximum sink current SI capabilities VBOOTx-VOUTx = 5.5 V 250 mA Full temperature range VS = VREG12 = 12 V VBOOTx-VOUTx = 12 V 350 600 mA TJ = 25 °C VS = VREG12 = 12 V VBOOTx-VOUTx = 12 V 300 mA Full temperature range I Maximum source current SO capabilities VS = VREG12 = 5.5 V VBOOTx-VOUTx = 5.5 V 300 mA TJ = 25 °C VS = VREG12 = 5.5 V VBOOTx-VOUTx = 5.5 V 250 mA Full temperature range VS = VREG12 = 12 V VBOOTx-VOUTx = 12 V 3.8 4.8 Ω Isource = 100 mA TJ = 25 °C RPMOS PMOS on resistance VS = VREG12 = 5.5 V VBOOTx-VOUTx = 5.5 V 6.1 Ω Isource = 100 mA Full temperature range VS = VREG12 = 12 V VBOOTx-VOUTx = 12 V 1.8 2.3 Ω Isink = 100 mA TJ = 25 °C RNMOS NMOS on resistance VS = VREG12 = 5.5 V VBOOTx-VOUTx = 5.5 V 3 Ω Isink = 100 mA Full temperature range OUTx = VS = 60 V 85 155 225 µA TJ = 25 °C IOUT,bias OUTx bias current OUTx = 0 V 85 155 225 µA TJ = 25 °C (1) 40 70 ns VS = VREG12 = 5.5 V t Input to output propagation on, toff delay VBOOTx-VOUTx = 5.5 V 120 ns Full temperature range
DS13472
-
Rev 1 page 7/32
Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Electrical data 2.1 Absolute maximum ratings 2.2 Recommended operating conditions 2.3 Thermal data 2.4 Electrical sensitivity characteristics 3 Electrical characteristics 4 Pin description 5 Device description 5.1 Gate drivers’ characteristics 5.2 12 V LDO linear regulator 5.2.1 Bootstrap section 5.2.1.1 Power-up and wake-up 5.2.1.2 Charging time and external bootstrap diodes 5.2.2 Externally provided gate driver’s supply voltage 5.3 Control logic 5.3.1 Deadtime 5.4 Standby mode 5.5 Undervoltage protection 5.6 VDS monitoring protection 5.7 Overcurrent comparator 5.8 Thermal protection 6 ESD protection strategy 7 Application example 8 Package information 9 Ordering information Revision history Contents List of tables List of figures
STDRIVE101 Electrical characteristics Symbol Parameter Test Condition Min. Typ. Max. Unit
VS = VREG12 = 5.5 V I Maximum sink current SI capabilities VBOOTx-VOUTx = 5.5 V 250 mA Full temperature range VS = VREG12 = 12 V VBOOTx-VOUTx = 12 V 350 600 mA TJ = 25 °C VS = VREG12 = 12 V VBOOTx-VOUTx = 12 V 300 mA Full temperature range I Maximum source current SO capabilities VS = VREG12 = 5.5 V VBOOTx-VOUTx = 5.5 V 300 mA TJ = 25 °C VS = VREG12 = 5.5 V VBOOTx-VOUTx = 5.5 V 250 mA Full temperature range VS = VREG12 = 12 V VBOOTx-VOUTx = 12 V 3.8 4.8 Ω Isource = 100 mA TJ = 25 °C RPMOS PMOS on resistance VS = VREG12 = 5.5 V VBOOTx-VOUTx = 5.5 V 6.1 Ω Isource = 100 mA Full temperature range VS = VREG12 = 12 V VBOOTx-VOUTx = 12 V 1.8 2.3 Ω Isink = 100 mA TJ = 25 °C RNMOS NMOS on resistance VS = VREG12 = 5.5 V VBOOTx-VOUTx = 5.5 V 3 Ω Isink = 100 mA Full temperature range OUTx = VS = 60 V 85 155 225 µA TJ = 25 °C IOUT,bias OUTx bias current OUTx = 0 V 85 155 225 µA TJ = 25 °C (1) 40 70 ns VS = VREG12 = 5.5 V t Input to output propagation on, toff delay VBOOTx-VOUTx = 5.5 V 120 ns Full temperature range
DS13472
-
Rev 1 page 7/32
Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Electrical data 2.1 Absolute maximum ratings 2.2 Recommended operating conditions 2.3 Thermal data 2.4 Electrical sensitivity characteristics 3 Electrical characteristics 4 Pin description 5 Device description 5.1 Gate drivers’ characteristics 5.2 12 V LDO linear regulator 5.2.1 Bootstrap section 5.2.1.1 Power-up and wake-up 5.2.1.2 Charging time and external bootstrap diodes 5.2.2 Externally provided gate driver’s supply voltage 5.3 Control logic 5.3.1 Deadtime 5.4 Standby mode 5.5 Undervoltage protection 5.6 VDS monitoring protection 5.7 Overcurrent comparator 5.8 Thermal protection 6 ESD protection strategy 7 Application example 8 Package information 9 Ordering information Revision history Contents List of tables List of figures