Datasheet PIC16F84A (Microchip) - 5

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PIC16F84A 2.0 MEMORY ORGANIZATION FIGURE 2-1: PROGRAM MEMORY MAP AND STACK - PIC16F84A
There are two memory blocks in the PIC16F84A. These are the program memory and the data memory. PC<12:0> Each block has its own bus, so that access to each CALL, RETURN 13 block can occur during the same oscillator cycle. RETFIE, RETLW Stack Level 1 The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that Stack Level 8 control the “core” are described here. The SFRs used RESET Vector 0000h to control the peripheral modules are described in the section discussing each individual peripheral module. Peripheral Interrupt Vector 0004h The data memory area also contains the data EEPROM memory. This memory is not directly mapped into the data memory, but is indirectly mapped. That is, ry an indirect address pointer specifies the address of the o m e c data EEPROM memory to read/write. The 64 bytes of a data EEPROM memory have the address range r Me e Sp s 0h-3Fh. More details on the EEPROM memory can be U found in Section 3.0. Additional information on device memory may be found in the PIC® Mid-Range Reference Manual, (DS33023).
2.1 Program Memory Organization
3FFh The PIC16FXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16F84A, the first 1K x 14 (0000h-03FFh) are physically implemented (Figure 2-1). Accessing a loca- tion above the physically implemented address will 1FFFh cause a wraparound. For example, for locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h, the instruction will be the same. The RESET vector is at 0000h and the interrupt vector is at 0004h.  2001-2013 Microchip Technology Inc. DS35007C-page 5 Document Outline 1.0 Device Overview FIGURE 1-1: PIC16F84A Block Diagram TABLE 1-1: PIC16F84A Pinout Description 2.0 Memory Organization 2.1 Program Memory Organization FIGURE 2-1: Program Memory Map and Stack - PIC16F84A 2.2 Data Memory Organization 2.2.1 General purpose Register File FIGURE 2-2: Register File Map - PIC16F84A 2.3 Special Function Registers TABLE 2-1: Special Function Register File Summary 2.3.1 STATUS Register Register 2-1: Status Register (Address 03h, 83h) 2.3.2 OPTION Register Register 2-2: OPTION Register (Address 81h) 2.3.3 INTCOn Register Register 2-3: INTCON Register (Address 0Bh, 8Bh) 2.4 PCL and PCLATH 2.4.1 Stack 2.5 Indirect Addressing; INDF and FSR Registers EXAMPLE 2-1: Indirect Addressing EXAMPLE 2-2: How to Clear RAM Using Indirect Addressing FIGURE 2-3: Direct/Indirect Addressing 3.0 Data EEPROM Memory Register 3-1: EECON1 Register (Address 88h) 3.1 Reading the EEPROM Data Memory EXAMPLE 3-1: Data EEPROM Read 3.2 Writing to the EEPROM Data Memory EXAMPLE 3-2: Data EEPROM Write 3.3 Write Verify EXAMPLE 3-3: Write Verify TABLE 3-1: Registers/Bits Associated with Data EEPROM 4.0 I/O Ports 4.1 PORTA and TRISA Registers EXAMPLE 4-1: Initializing PORTA FIGURE 4-1: Block Diagram of Pins RA3:RA0 FIGURE 4-2: Block Diagram of Pin RA4 TABLE 4-1: PORTA Functions TABLE 4-2: Summary of Registers Associated With PORTA 4.2 PORTB and TRISB Registers EXAMPLE 4-2: Initializing PORTB FIGURE 4-3: Block Diagram of Pins RB7:RB4 FIGURE 4-4: Block Diagram of Pins RB3:RB0 TABLE 4-3: PORTB Functions TABLE 4-4: Summary of Registers Associated With PORTB 5.0 Timer0 Module 5.1 Timer0 Operation 5.2 Prescaler FIGURE 5-1: Timer0 Block Diagram 5.2.1 Switching Prescaler ASSIGnment 5.3 Timer0 Interrupt FIGURE 5-2: Block Diagram of the Timer0/WDT Prescaler TABLE 5-1: Registers Associated with Timer0 6.0 Special Features of the CPU 6.1 Configuration Bits Register 6-1: PIC16F84A Configuration Word 6.2 Oscillator Configurations 6.2.1 Oscillator Types 6.2.2 Crystal Oscillator/CERAmic Resonators FIGURE 6-1: Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration) FIGURE 6-2: External Clock Input Operation (HS, XT or LP OSC Configuration) TABLE 6-1: Capacitor Selection for Ceramic Resonators TABLE 6-2: Capacitor Selection for Crystal Oscillator 6.2.3 RC Oscillator FIGURE 6-3: RC Oscillator Mode 6.3 Reset FIGURE 6-4: Simplified Block Diagram of On-Chip Reset Circuit TABLE 6-3: Reset Condition for Program Counter and the STATUS Register TABLE 6-4: Reset Conditions for All Registers 6.4 Power-on Reset (POR) 6.5 Power-up Timer (PWRT) 6.6 Oscillator Start-up Timer (OST) FIGURE 6-5: External Power-on Reset Circuit (For Slow Vdd Power-up) FIGURE 6-6: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1 FIGURE 6-7: Time-out Sequence on Power-up (MCLR Not Tied To Vdd): Case 2 FIGURE 6-8: Time-out Sequence on Power-up (MCLR Tied to Vdd): Fast Vdd Rise Time FIGURE 6-9: Time-Out Sequence on Power-Up (MCLR Tied to Vdd): Slow Vdd Rise Time 6.7 Time-out Sequence and Power-down Status Bits (TO/PD) TABLE 6-5: Time-out in Various Situations TABLE 6-6: STATUS bits and Their Significance 6.8 Interrupts FIGURE 6-10: Interrupt Logic 6.8.1 INT Interrupt 6.8.2 TMR0 Interrupt 6.8.3 PORTB Interrupt 6.8.4 Data EEPROM Interrupt 6.9 Context Saving During Interrupts EXAMPLE 6-1: Saving STATUS and W Registers in RAM 6.10 Watchdog Timer (WDT) 6.10.1 WDT Period 6.10.2 WDT Programming Considerations FIGURE 6-11: Watchdog Timer Block Diagram TABLE 6-7: Summary of Registers Associated With the Watchdog Timer 6.11 Power-down Mode (SLEEP) 6.11.1 SLEEP 6.11.2 Wake-up from SLEEP FIGURE 6-12: Wake-up From Sleep Through Interrupt 6.11.3 Wake-Up Using Interrupts 6.12 Program Verification/Code Protection 6.13 ID Locations 6.14 In-Circuit Serial Programming 7.0 Instruction Set Summary TABLE 7-1: Opcode Field Descriptions FIGURE 7-1: General Format for Instructions TABLE 7-2: PIC16CXXX Instruction Set 7.1 Instruction Descriptions 8.0 Development Support 9.0 Electrical Characteristics FIGURE 9-1: PIC16F84A-20 Voltage-Frequency Graph FIGURE 9-2: PIC16LF84A-04 Voltage- Frequency Graph FIGURE 9-3: PIC16F84A-04 Voltage- Frequency Graph 9.1 DC Characteristics 9.2 DC Characteristics: PIC16F84A-04 (Commercial, Industrial) PIC16F84A-20 (Commercial, Industrial) PIC16LF84A-04 (Commercial, Industrial) 9.3 AC (Timing) Characteristics 9.3.1 Timing Parameter Symbology 9.3.2 Timing Conditions TABLE 9-1: Temperature and Voltage Specifications - AC FIGURE 9-4: Parameter Measurement Information FIGURE 9-5: Load Conditions 9.3.3 Timing Diagrams and Specifications FIGURE 9-6: External Clock Timing TABLE 9-2: External Clock Timing Requirements FIGURE 9-7: CLKOUT and I/O Timing TABLE 9-3: CLKOUT and I/O Timing Requirements FIGURE 9-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing TABLE 9-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements FIGURE 9-9: Timer0 Clock Timings TABLE 9-5: Timer0 Clock Requirements 10.0 DC/AC Characteristic Graphs FIGURE 10-1: Typical Idd vs. Fosc OVER Vdd (HS Mode, 25°C) FIGURE 10-2: Maximum Idd vs. Fosc OVER Vdd (HS Mode, -40° to +125°C) FIGURE 10-3: Typical Idd vs. Fosc OVER Vdd (XT Mode, 25°C) FIGURE 10-4: Maximum Idd vs. Fosc OVER Vdd (XT Mode, -40° to +125°C) FIGURE 10-5: Typical Idd vs. Fosc OVER Vdd (LP Mode, 25°C) FIGURE 10-6: Maximum Idd vs. Fosc OVER Vdd (LP Mode, -40° to +125°C) FIGURE 10-7: Average Fosc vs. Vdd for R (RC Mode, C = 22 pF, 25°C) FIGURE 10-8: Average Fosc vs. Vdd for R (RC Mode, C = 100 pF, 25°C) FIGURE 10-9: Average Fosc vs. Vdd for R (RC Mode, C = 300 pF, 25°C) FIGURE 10-10: Ipd vs. Vdd (Sleep Mode, all peripherals disabled) FIGURE 10-11: Ipd vs. Vdd (WDT Mode) FIGURE 10-12: Typical, Minimum, and Maximum WDT Period vs. Vdd over Temp FIGURE 10-13: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40°C to +125°C) FIGURE 10-14: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40°C to +125°C) FIGURE 10-15: Typical, Minimum and Maximum Vol vs. Iol (Vdd = 5V, -40°C to +125°C) FIGURE 10-16: Typical, Minimum and Maximum Vol vs. Iol (Vdd = 3V, -40°C to +125°C) FIGURE 10-17: Minimum and Maximum Vin vs. Vdd, (TTL Input, -40°C to +125°C) FIGURE 10-18: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to +125°C) 11.0 Packaging Information 11.1 Package Marking Information Appendix A: Revision History Appendix B: Conversion Considerations Appendix C: Migration from Baseline to Mid-range Devices A B C D E F I M O P R S T W Z The Microchip Web Site Customer Change Notification Service Customer Support Reader Response Corporate Office Atlanta Boston Chicago Cleveland Fax: 216-447-0643 Dallas Detroit Indianapolis Toronto Fax: 852-2401-3431 Australia - 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