Datasheet K6R1016V1D (Samsung) - 9

for AT&T K6R1016V1D CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(4)
(UB, LB Controlled) tWC
Address
tAW t t WR(5) CW(3)
CS
tBW
UB, LB
tAS(4) tWP(2)
WE
tDW tDH High-Z
Data in
Valid Data tBLZ tWHZ(6) High-Z High-Z(8)
Data out NOTES
(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE going low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION I/O Pin CS WE OE LB UB Mode Supply Current I/O1~I/O8 I/O9~I/O16
H X X* X X Not Select High-Z High-Z ISB, ISB1 L H H X X Output Disable High-Z High-Z ICC L X X H H L H DOUT High-Z L H L H L Read High-Z DOUT ICC L L DOUT DOUT L H DIN High-Z L L X H L Write High-Z DIN ICC L L DIN DIN * X means Don′t Care.
Revision 3.0
- 9 -
June 2002