Datasheet ADSP-21065L-EP (Analog Devices) - 5

Enhanced Product ADSP-21065L-EP PIN FUNCTION DESCRIPTIONS
The ADSP-21065L-EP pin definitions are listed below. Inputs Unused inputs should be tied or pulled to VDD or GND, except identified as synchronous (S) must meet timing requirements for ADDR23–0, DATA31–0, FLAG11–0, SW, and inputs that have with respect to CLKIN (or with respect to TCK for TMS, TDI). internal pull-up or pull-down resistors (CPA, ACK, DTxX, Inputs identified as asynchronous (A) can be asserted asynchro- DRxX, TCLKx, RCLKx, TMS, and TDI)—these pins can be left nously to CLKIN (or to TCK for TRST). floating. These pins have a logic-level hold circuit that prevents the input from floating internally.
Table 2. Pin Descriptions Pin Type Function
ADDR23–0 I/O/T
External Bus Address.
The ADSP-21065L-EP outputs addresses for external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes of the IOP registers of the other ADSP-21065L-EP processors. The ADSP-21065L-EP inputs addresses when a host processor or multiprocessing bus master is reading or writing its IOP registers. DATA31–0 I/O/T
External Bus Data.
The ADSP-21065L-EP inputs and outputs data and instructions on these pins. The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-point data over bits 31–0. 16-bit short word data is transferred over bits 15–0 of the bus. Pull-up resistors on unused DATA pins are not necessary. MS3–0 I/O/T
Memory Select Lines.
These lines are asserted as chip selects for the corresponding banks of external memory. Internal ADDR25–24 are decoded into MS3–0. The MS3-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring the MS3–0 lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. Additionally, an MS3–0 line which is mapped to SDRAM may be asserted even when no SDRAM access is active. In a multiprocessor system, the MS3–0 lines are output by the bus master. RD I/O/T
Memory Read Strobe.
This pin is asserted when the ADSP-21065L-EP reads from external memory devices or from the IOP register of another ADSP-21065L-EP. External devices (including another ADSP-21065L-EP) must assert RD to read from the ADSP-21065L-EP’s IOP registers. In a multiprocessing system, RD is output by the bus master and is input by another ADSP-21065L-EP. WR I/O/T
Memory Write Strobe.
This pin is asserted when the ADSP-21065L-EP writes to external memory devices or to the IOP register of another ADSP-21065L-EP. External devices must assert WR to write to the ADSP-21065L-EP’s IOP registers. In a multiprocessing system, WR is output by the bus master and is input by the other ADSP-21065L-EP. SW I/O/T
Synchronous Write Select.
This signal interfaces the ADSP-21065L-EP to synchronous memory devices (including another ADSP-21065L-EP). The ADSP-21065L-EP asserts SW to provide an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output by the bus master and is input by the other ADSP-21065L-EP to determine if the multiprocessor access is a read or write. SW is asserted at the same time as the address output. ACK I/O/S
Memory Acknowledge.
External devices can deassert ACK to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-21065L-EP deasserts ACK as an output to add waitstates to a synchronous access of its IOP registers. In a multiprocessing system, a slave ADSP-21065L-EP deasserts the bus master’s ACK input to add wait state(s) to an access of its IOP registers. The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was last driven. SBTS I/S
Suspend Bus Three-State.
External devices can assert SBTS to place the external bus address, data, selects, and strobes—but not SDRAM control pins—in a high impedance state for the following cycle. If the ADSP-21065L-EP attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not finish until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21065L-EP deadlock. IRQ2–0 I/A
Interrupt Request Lines.
May be either edge-triggered or level-sensitive. A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, T = Three-State (when SBTS is asserted, or when the ADSP-21065L-EP is a bus slave) Rev. B | Page 5 of 14 | September 2017 Document Outline Summary Enhanced Product (EP) Features Features Table of Contents Revision History General Description Pin Function Descriptions Specifications Operating Conditions Absolute Maximum Ratings ESD Caution Package Marking Information Environmental Conditions Thermal Characteristics 208-LEAD MQFP Pin Configuration Outline Dimensions Ordering Guide