Datasheet ADSP-21065L-EP (Analog Devices)

SHARC DSP Microcomputer Enhanced Product ADSP-21065L-EP SUMMARY ENHANCED PRODUCT (EP) FEATURES High performance signal computer for communications, Supports defense and aerospace applications (AQEC audio, automotive, instrumentation, medical, military, and standard) industrial applications Extended temperature range –55°C to +110°C Super Harvard Architecture Computer (SHARC) — four inde- Controlled manufacturing baseline pendent buses for dual data, instruction, and I/O fetch on a One package assembly/test site single cycle One wafer fabrication site 32-bit fixed-point arithmetic; 32-bit and 40-bit floating- Enhanced product change notification point arithmetic Qualification data available upon request 544K bits on-chip SRAM memory and integrated I/O peripheral I2S support, for eight simultaneous receive and transmit channels CORE PROCESSOR DUAL-PORTED SRAM INSTRUCTION TWO INDEPENDENT JTAG 7 CACHE DUAL-PORTED BLOCKS TEST AND 32 × 48-BIT PROCESSOR PORT I/O PORT LOCK 0 EMULATION B ADDR DATA DATA ADDR LOCK 1 B ADDR DATA ADDR DATA EXTERNAL DAG1 DAG2 PROGRAM PORT 8 × 4 × 32 8 × 4 × 24 SEQUENCER SDRAM IOD IOA INTERFACE 24 48 17 PM ADDRESS BUS 24 ADDR BUS DM ADDRESS BUS 32 MUX MULTIPROCESSOR INTERFACE PM DATA BUS 48 BUS 32 DATA BUS CONNECT DM DATA BUS 40 MUX (PX) HOST PORT
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DATA IOP DMA 4 REGISTER REGISTERS CONTROLLER FILE (MEMORY MAPPED) (2 Rx, 2Tx) 16 MULTIPLIER
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40-BIT BARREL SPORT 0 ALU CONTROL, SHIFTER (I2S) STATUS, TIMER, (2 Rx, 2Tx) AND SPORT 1 DATA BUFFERS (I2S) I/O PROCESSOR
Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
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Document Outline Summary Enhanced Product (EP) Features Features Table of Contents Revision History General Description Pin Function Descriptions Specifications Operating Conditions Absolute Maximum Ratings ESD Caution Package Marking Information Environmental Conditions Thermal Characteristics 208-LEAD MQFP Pin Configuration Outline Dimensions Ordering Guide