Datasheet MAX1086, MAX1087, MAX1088, MAX1089 (Maxim) - 7

150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 and TDFN MAX1086–MAX1089 Pin Description NAME PIN MAX1086 MAX1088 FUNCTION MAX1087 MAX1089
Positive Supply Voltage. +2.7V to +3.6V (MAX1087/MAX1089); +4.75V to +5.25V 1 VDD VDD (MAX1086/MAX1088). Bypass with a 0.1µF capacitor to GND. 2 AIN1 AIN+ Analog Input Channel 1 (MAX1086/MAX1087) or Positive Analog Input (MAX1088/MAX1089) 3 AIN2 AIN- Analog Input Channel 2 (MAX1086/MAX1087) or Negative Analog Input (MAX1088/MAX1089) 4 GND GND Ground External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1µF 5 REF REF capacitor to GND. Conversion Start. A rising edge powers-up the IC and places it in track mode. At the falling 6 CNVST CNVST edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the input channel (MAX1086/MAX1087) or input polarity (MAX1088/MAX1089). Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a 7 DOUT DOUT conversion and presents the MSB at the completion of a conversion. DOUT goes high- impedance once data has been fully clocked out. 8 SCLK SCLK Serial Clock Input. Clocks out data at DOUT MSB first. — EP — Exposed Pad (TDFN only). Connect the exposed pad to ground or leave unconnected.
Detailed Description
The serial interface provides easy interfacing to micro- processors (µPs). Figure 3 shows the simplified internal The MAX1086–MAX1089 analog-to-digital converters structure for the MAX1086/MAX1087 (2–channels, sin- (ADCs) use a successive-approximation conversion (SAR) gle-ended) and the MAX1088/MAX1089 (1–channel, technique and an on-chip track-and-hold (T/H) structure to true-differential). convert an analog signal into a 10-bit digital result.
True-Differential Analog Input Track/Hold
The equivalent circuit of Figure 4 shows the MAX1086–MAX1089’s input architecture which is com- posed of a T/H, input multiplexer, comparator, and MAX1086–MAX1089 switched-capacitor DAC. The T/H enters its tracking OSCILLATOR mode on the rising edge of CNVST. The positive input CNVST capacitor is connected to AIN1 or AIN2 (MAX1086/ INPUT SHIFT SCLK REGISTER MAX1087) or AIN+ (MAX1088/MAX1089). The negative input capacitor is connected to GND (MAX1086/ MAX1087) or AIN- (MAX1088/MAX1089). The T/H enters CONTROL its hold mode on the falling edge of CNVST and the dif- ference between the sampled positive and negative AIN1 input voltages is converted. The time required for the T/H 10-BIT DOUT (AIN+) to acquire an input signal is determined by how quickly T/H SAR AIN2 ADC its input capacitance is charged. If the input signal’s (AIN-) source impedance is high, the acquisition time length- ens, and CNVST must be held high for a longer period of REF time. The acquisition time, tACQ, is the maximum time ( ) ARE FOR MAX1088/MAX1089 needed for the signal to be acquired, plus the power-up time. It is calculated by the following equation: Figure 3. Simplified Functional Diagram tACQ = 7 x (RS + RIN) x 24pF + tPWR
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