Datasheet MAX1086, MAX1087, MAX1088, MAX1089 (Maxim) - 8

150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 and TDFN
DOUT after 3.7µs. Data can then be clocked out using SCLK. If all 12 bits of data are not clocked out before REF DAC AIN2 CNVST is driven high, AIN2 will be selected for the next GND AIN1(AIN+) conversion. CIN+ COMPARATOR
Selecting Unipolar or Bipolar Conversions
+
(MAX1088/MAX1089)
HOLD Initiate true-differential conversions with the - MAX1088/MAX1089’s unipolar and bipolar modes, CIN- using the CNVST pin. AIN+ and AIN- are sampled at RIN- RIN+ GND(AIN-) the falling edge of CNVST. In unipolar mode, AIN+ can exceed AIN- by up to VREF. The output format is HOLD HOLD straight binary. In bipolar mode, either input can TRACK V exceed the other by up to VREF/2. The output format is DD/2 *( ) APPLIES TO MAX1088/1089 two’s complement.
Note:
In both modes, AIN+ and AIN- must not exceed Figure 4. Equivalent Input Circuit VDD by more than 50mV or be lower than GND by more than 50mV.
MAX1086–MAX1089
where RIN = 1.5kΩ, RS is the source impedance of the If unipolar mode is desired (Figure 5a), drive CNVST input signal, and tPWR = 1µs is the power-up time of the high to power-up the ADC and place the T/H in track device. mode with AIN+ and AIN- connected to the input
Note:
tACQ is never less than 1.4µs and any source capacitors. Hold CNVST high for tACQ to fully acquire impedance below 300Ω does not significantly affect the the signal. Drive CNVST low to place the T/H in hold ADC‘s AC performance. A high impedance source can mode. The ADC will then perform a conversion and be accommodated either by lengthening tACQ or by shutdown automatically. The MSB is available at DOUT placing a 1µF capacitor between the positive and neg- after 3.7µs. Data can then be clocked out using SCLK. ative analog inputs. Be sure to clock out all 12 bits (the 10-bit result plus two sub-bits) of data before driving CNVST high for the
Selecting AIN1 or AIN2
next conversion. If all 12 bits of data are not clocked
(MAX1086/MAX1087)
out before CNVST is driven high, bipolar mode will be Select between the MAX1086/MAX1087’s two positive selected for the next conversion. input channels using the CNVST pin. If AIN1 is desired If bipolar mode is desired (Figure 5b), drive CNVST (Figure 5a), drive CNVST high to power-up the ADC high for at least 30ns. Next, drive it low for at least 30ns and place the T/H in track mode with AIN1 connected and then high again. This will place the T/H in track to the positive input capacitor. Hold CNVST high for mode with AIN+ and AIN- connected to the input tACQ to fully acquire the signal. Drive CNVST low to capacitors. Now hold CNVST high for t place the T/H in hold mode. The ADC will then perform ACQ to fully acquire the signal. Drive CNVST low to place the T/H in a conversion and shutdown automatically. The MSB is hold mode. The ADC will then perform a conversion available at DOUT after 3.7µs. Data can then be and shutdown automatically. The MSB is available at clocked out using SCLK. Be sure to clock out all 12 bits DOUT after 3.7µs. Data can then be clocked out using of data (the 10-bit result plus two sub-bits) before dri- SCLK. If all 12 bits of data are not clocked out before ving CNVST high for the next conversion. If all 12 bits of CNVST is driven high, bipolar mode will be selected for data are not clocked out before CNVST is driven high, the next conversion. AIN2 will be selected for the next conversion. If AIN2 is desired (Figure 5b), drive CNVST high for at
Input Bandwidth
least 30ns. Next, drive it low for at least 30ns, and then The ADCs input tracking circuitry has a 1MHz small- high again. This will power-up the ADC and place the signal bandwidth, so it is possible to digitize high- T/H in track mode with AIN2 connected to the positive speed transient events and measure periodic signals input capacitor. Now hold CNVST high for tACQ to fully with bandwidths exceeding the ADC’s sampling rate by acquire the signal. Drive CNVST low to place the T/H in using undersampling techniques. To avoid high fre- hold mode. The ADC will then perform a conversion quency signals being aliased into the frequency band and shutdown automatically. The MSB is available at of interest, anti-alias filtering is recommended.
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