Datasheet ADCMP561, ADCMP562 (Analog Devices)

Dual High Speed PECL Comparators Data Sheet ADCMP561 /ADCMP562 FEATURES FUNCTIONAL BLOCK DIAGRAM Differential PECL-compatible outputs HYS* 700 ps propagation delay input to output NONINVERTING 75 ps propagation delay dispersion Q OUTPUT INPUT Input common-mode range: –2.0 V to +3.0 V ADCMP561/ ADCMP562 Robust input protection INVERTING Q OUTPUT Differential latch control INPUT Internal latch pull-up resistors Power supply rejection greater than 85 dB LATCH ENABLE LATCH ENABLE INPUT INPUT 700 ps minimum pulse width *ADCMP562 ONLY
04687-0-001
1.5 GHz equivalent input rise time bandwidth
Figure 1.
Typical output rise/fall time of 500 ps ESD protection > 4 kV HBM, >200 V MM QA 1 16 QB Programmable hysteresis QA 2 15 QB APPLICATIONS V 3 14 GND DD ADCMP561 Automatic test equipment LEA 4 13 LEB TOP VIEW High speed instrumentation LEA 5 (Not to Scale) 12 LEB Scope and logic analyzer front ends V 6 11 V EE CC Window comparators –INA 7 10 –INB +INB High speed line receivers +INA 8 9
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Threshold detection
Figure 2. ADCMP561 16-Lead QSOP Pin Configuration
Peak detection High speed triggers V 1 20 DD VDD Patient diagnostics QA 2 19 QB Disk drive read channel detection QA 3 18 QB Hand-held test instruments V 4 ADCMP562 17 DD GND Zero-crossing detectors TOP VIEW LEA 5 16 LEB (Not to Scale) Line receivers and signal restoration LEA 6 15 LEB Clock drivers V 7 14 EE VCC –INA 8 13 –INB +INA 9 12 +INB HYSA 10 11 HYSB
04687-0-003 Figure 3. ADCMP562 20-Lead QSOP Pin Configuration
GENERAL DESCRIPTION
The ADCMP561/ADCMP562 are high speed comparators to +3.0 V. Outputs are complementary digital signals that are fully fabricated on Analog Devices, Inc., proprietary XFCB process. The compatible with PECL 10 K and 10 KH logic families. The outputs devices feature a 700 ps propagation delay with less than 75 ps provide sufficient drive current to directly drive transmission lines overdrive dispersion. Dispersion, a measure of the difference in terminated in 50 Ω to VDD − 2 V. A latch input, which is included, propagation delay under differing overdrive conditions, is a permits tracking, track-and-hold, or sample-and-hold modes of particularly important characteristic of comparators. A separate operation. The latch input pins contain internal pul -ups that set programmable hysteresis pin is available on the ADCMP562. the latch in tracking mode when left open. A differential input stage permits consistent propagation delay with The ADCMP561/ADCMP562 are specified over the industrial a wide variety of signals in the common-mode range from −2.0 V temperature range (−40°C to +85°C).
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TIMING INFORMATION APPLICATIONS INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE